backend\A64\emit_a64_data_processing.cpp:Implement ops
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SachinVin
xperia64
parent
ddf33c425b
commit
85fa3096dd
@ -13,4 +13,182 @@
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#include "frontend/ir/opcodes.h"
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namespace Dynarmic::BackendA64 {
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void EmitA64::EmitPack2x32To1x64(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ARM64Reg lo = ctx.reg_alloc.UseScratchGpr(args[0]);
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ARM64Reg hi = ctx.reg_alloc.UseScratchGpr(args[1]);
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// code.MOV(lo, DecodeReg(lo)); // Zero extend to 64-bits
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code.ORR(lo, lo, hi, ArithOption{hi, ST_LSL, 32});
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ctx.reg_alloc.DefineValue(inst, lo);
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}
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//void EmitA64::EmitPack2x64To1x128(EmitContext& ctx, IR::Inst* inst) {
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// auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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// Xbyak::Reg64 lo = ctx.reg_alloc.UseGpr(args[0]);
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// Xbyak::Reg64 hi = ctx.reg_alloc.UseGpr(args[1]);
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// Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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//
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// if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
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// code.movq(result, lo);
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// code.pinsrq(result, hi, 1);
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// } else {
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// Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
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// code.movq(result, lo);
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// code.movq(tmp, hi);
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// code.punpcklqdq(result, tmp);
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// }
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//
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// ctx.reg_alloc.DefineValue(inst, result);
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//}
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void EmitA64::EmitLeastSignificantWord(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ctx.reg_alloc.DefineValue(inst, args[0]);
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}
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void EmitA64::EmitMostSignificantWord(EmitContext& ctx, IR::Inst* inst) {
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auto carry_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ARM64Reg result = ctx.reg_alloc.UseScratchGpr(args[0]);
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if (carry_inst) {
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ARM64Reg carry = ctx.reg_alloc.ScratchGpr();
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code.UBFX(carry, result, 31, 1);
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ctx.reg_alloc.DefineValue(carry_inst, carry);
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ctx.EraseInstruction(carry_inst);
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}
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code.LSR(result, result, 32);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitLeastSignificantHalf(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ctx.reg_alloc.DefineValue(inst, args[0]);
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}
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void EmitA64::EmitLeastSignificantByte(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ctx.reg_alloc.DefineValue(inst, args[0]);
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}
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void EmitA64::EmitMostSignificantBit(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.UseScratchGpr(args[0]));
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// TODO: Flag optimization
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code.LSR(result,result, 31);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitIsZero32(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.UseScratchGpr(args[0]));
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// TODO: Flag optimization
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code.CMP(result, WZR);
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code.CSET(result, CC_EQ);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitIsZero64(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ARM64Reg result = ctx.reg_alloc.UseScratchGpr(args[0]);
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// TODO: Flag optimization
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code.CMP(result, WZR);
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code.CSET(result, CC_EQ);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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//void EmitA64::EmitTestBit(EmitContext& ctx, IR::Inst* inst) {
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// auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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// Xbyak::Reg64 result = ctx.reg_alloc.UseScratchGpr(args[0]);
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// ASSERT(args[1].IsImmediate());
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// // TODO: Flag optimization
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// code.bt(result, args[1].GetImmediateU8());
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// code.setc(result.cvt8());
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// ctx.reg_alloc.DefineValue(inst, result);
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//}
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static void EmitConditionalSelect(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, int bitsize) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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Arm64Gen::ARM64Reg nzcv = ctx.reg_alloc.ScratchGpr();
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Arm64Gen::ARM64Reg then_ = ctx.reg_alloc.UseGpr(args[1]);
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Arm64Gen::ARM64Reg else_ = ctx.reg_alloc.UseScratchGpr(args[2]);
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then_ = bitsize == 64 ? then_ : DecodeReg(then_);
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else_ = bitsize == 64 ? else_ : DecodeReg(else_);
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code.LDR(INDEX_UNSIGNED, DecodeReg(nzcv), X28, code.GetJitStateInfo().offsetof_CPSR_nzcv);
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// TODO: Flag optimization
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code._MSR(FIELD_NZCV, nzcv);
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switch (args[0].GetImmediateCond()) {
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case IR::Cond::EQ: //z
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code.CSEL(else_, else_, then_ , CC_EQ);
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break;
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case IR::Cond::NE: //!z
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code.CSEL(else_, else_, then_, CC_NEQ);
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break;
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case IR::Cond::CS: //c
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code.CSEL(else_, else_, then_, CC_CS);
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break;
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case IR::Cond::CC: //!c
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code.CSEL(else_, else_, then_ , CC_CC);
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break;
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case IR::Cond::MI: //n
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code.CSEL(else_, else_, then_, CC_MI);
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break;
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case IR::Cond::PL: //!n
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code.CSEL(else_, else_, then_, CC_PL);
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break;
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case IR::Cond::VS: //v
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code.CSEL(else_, else_, then_, CC_VS);
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break;
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case IR::Cond::VC: //!v
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code.CSEL(else_, else_, then_, CC_VC);
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break;
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case IR::Cond::HI: //c & !z
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code.CSEL(else_, else_, then_, CC_HI);
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break;
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case IR::Cond::LS: //!c | z
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code.CSEL(else_, else_, then_, CC_LS);
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break;
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case IR::Cond::GE: // n == v
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code.CSEL(else_, else_, then_, CC_GE);
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break;
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case IR::Cond::LT: // n != v
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code.CSEL(else_, else_, then_, CC_LT);
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break;
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case IR::Cond::GT: // !z & (n == v)
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code.CSEL(else_, else_, then_, CC_GT);
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break;
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case IR::Cond::LE: // z | (n != v)
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code.CSEL(else_, else_, then_, CC_LE);
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break;
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case IR::Cond::AL:
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case IR::Cond::NV:
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code.MOV(else_, then_);
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break;
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default:
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ASSERT_MSG(false, "Invalid cond {}", static_cast<size_t>(args[0].GetImmediateCond()));
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}
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ctx.reg_alloc.DefineValue(inst, else_);
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}
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void EmitA64::EmitConditionalSelect32(EmitContext& ctx, IR::Inst* inst) {
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EmitConditionalSelect(code, ctx, inst, 32);
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}
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void EmitA64::EmitConditionalSelect64(EmitContext& ctx, IR::Inst* inst) {
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EmitConditionalSelect(code, ctx, inst, 64);
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}
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void EmitA64::EmitConditionalSelectNZCV(EmitContext& ctx, IR::Inst* inst) {
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EmitConditionalSelect(code, ctx, inst, 32);
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}
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} // namespace Dynarmic::BackendA64
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@ -87,20 +87,20 @@ OPCODE(GetLowerFromOp, U128, Opaq
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OPCODE(NZCVFromPackedFlags, NZCV, U32 )
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// Calculations
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//OPCODE(Pack2x32To1x64, U64, U32, U32 )
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OPCODE(Pack2x32To1x64, U64, U32, U32 )
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//OPCODE(Pack2x64To1x128, U128, U64, U64 )
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//OPCODE(LeastSignificantWord, U32, U64 )
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//OPCODE(MostSignificantWord, U32, U64 )
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//OPCODE(LeastSignificantHalf, U16, U32 )
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//OPCODE(LeastSignificantByte, U8, U32 )
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//OPCODE(MostSignificantBit, U1, U32 )
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//OPCODE(IsZero32, U1, U32 )
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//OPCODE(IsZero64, U1, U64 )
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OPCODE(LeastSignificantWord, U32, U64 )
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OPCODE(MostSignificantWord, U32, U64 )
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OPCODE(LeastSignificantHalf, U16, U32 )
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OPCODE(LeastSignificantByte, U8, U32 )
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OPCODE(MostSignificantBit, U1, U32 )
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OPCODE(IsZero32, U1, U32 )
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OPCODE(IsZero64, U1, U64 )
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//OPCODE(TestBit, U1, U64, U8 )
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//OPCODE(ConditionalSelect32, U32, Cond, U32, U32 )
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//OPCODE(ConditionalSelect64, U64, Cond, U64, U64 )
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//OPCODE(ConditionalSelectNZCV, NZCV, Cond, NZCV, NZCV )
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//OPCODE(LogicalShiftLeft32, U32, U32, U8, U1 )
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OPCODE(ConditionalSelect32, U32, Cond, U32, U32 )
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OPCODE(ConditionalSelect64, U64, Cond, U64, U64 )
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OPCODE(ConditionalSelectNZCV, NZCV, Cond, NZCV, NZCV )
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//OPCODE(LogicalShiftLeft64, U64, U64, U8 )
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//OPCODE(LogicalShiftRight32, U32, U32, U8, U1 )
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//OPCODE(LogicalShiftRight64, U64, U64, U8 )
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