From 887732d8a8d82c0b2b6a4369cc5311da265b4354 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Thu, 18 Jun 2020 11:28:12 -0400
Subject: [PATCH] A32: Implement ASIMD VSRI
---
src/frontend/A32/decoder/asimd.inc | 2 +-
.../translate/impl/asimd_two_regs_shift.cpp | 27 +++++++++++++++++++
.../A32/translate/impl/translate_arm.h | 1 +
3 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc
index 8388b4e2..63aa28be 100644
--- a/src/frontend/A32/decoder/asimd.inc
+++ b/src/frontend/A32/decoder/asimd.inc
@@ -62,7 +62,7 @@ INST(asimd_SHR, "SHR", "1111001U1Diiiiiidddd000
INST(asimd_SRA, "SRA", "1111001U1Diiiiiidddd0001LQM1mmmm") // ASIMD
INST(asimd_VRSHR, "VRSHR", "1111001U1Diiiiiidddd0010LQM1mmmm") // ASIMD
INST(asimd_VRSRA, "VRSRA", "1111001U1Diiiiiidddd0011LQM1mmmm") // ASIMD
-//INST(asimd_VSRI, "VSRI", "111100111-vvv-------0100LB-1----") // ASIMD
+INST(asimd_VSRI, "VSRI", "111100111Diiiiiidddd0100LQM1mmmm") // ASIMD
INST(asimd_VSHL, "VSHL", "111100101Diiiiiidddd0101LQM1mmmm") // ASIMD
//INST(asimd_VSLI, "VSLI", "111100111-vvv-------0101LB-1----") // ASIMD
//INST(asimd_VQSHL, "VQSHL" , "1111001U1-vvv-------011xLB-1----") // ASIMD
diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
index 65cbaf47..c5ad9a34 100644
--- a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
+++ b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
@@ -99,6 +99,33 @@ bool ArmTranslatorVisitor::asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, b
Accumulating::Accumulate, Rounding::Round);
}
+bool ArmTranslatorVisitor::asimd_VSRI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) {
+ if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
+ return UndefinedInstruction();
+ }
+
+ // Technically just a related encoding (One register and modified immediate instructions)
+ if (!L && Common::Bits<3, 5>(imm6) == 0) {
+ return UndefinedInstruction();
+ }
+
+ const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, L, imm6);
+ const u64 mask = shift_amount == esize ? 0 : Common::Ones<u64>(esize) >> shift_amount;
+
+ const auto d = ToVector(Q, Vd, D);
+ const auto m = ToVector(Q, Vm, M);
+
+ const auto reg_m = ir.GetVector(m);
+ const auto reg_d = ir.GetVector(d);
+
+ const auto shifted = ir.VectorLogicalShiftRight(esize, reg_m, static_cast<u8>(shift_amount));
+ const auto mask_vec = ir.VectorBroadcast(esize, I(esize, mask));
+ const auto result = ir.VectorOr(ir.VectorAnd(reg_d, ir.VectorNot(mask_vec)), shifted);
+
+ ir.SetVector(d, result);
+ return true;
+}
+
bool ArmTranslatorVisitor::asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h
index aeb91380..905ccf09 100644
--- a/src/frontend/A32/translate/impl/translate_arm.h
+++ b/src/frontend/A32/translate/impl/translate_arm.h
@@ -456,6 +456,7 @@ struct ArmTranslatorVisitor final {
bool asimd_SRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VRSHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
+ bool asimd_VSRI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
// Advanced SIMD two register, miscellaneous