From 99728efc1becc0e59870160e570e3fdeef84d238 Mon Sep 17 00:00:00 2001
From: SachinVin <sachinvinayak2000@gmail.com>
Date: Mon, 15 Jul 2019 21:03:41 +0530
Subject: [PATCH] a64 emitter: Fix LDR literal

---
 src/backend/A64/emitter/a64_emitter.cpp | 12 ++++++------
 src/backend/A64/emitter/a64_emitter.h   |  8 ++++----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/backend/A64/emitter/a64_emitter.cpp b/src/backend/A64/emitter/a64_emitter.cpp
index c387b37a..d7edba46 100644
--- a/src/backend/A64/emitter/a64_emitter.cpp
+++ b/src/backend/A64/emitter/a64_emitter.cpp
@@ -667,16 +667,16 @@ void ARM64XEmitter::EncodeLogicalInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM
             (LogicalEnc[instenc][1] << 21) | Shift.GetData() | (Rm << 16) | (Rn << 5) | Rd);
 }
 
-void ARM64XEmitter::EncodeLoadRegisterInst(u32 bitop, ARM64Reg Rt, u32 imm) {
+void ARM64XEmitter::EncodeLoadRegisterInst(u32 bitop, ARM64Reg Rt, s32 imm) {
     bool b64Bit = Is64Bit(Rt);
     bool bVec = IsVector(Rt);
 
-    ASSERT_MSG(!(imm & 0xFFFFF), "%s: offset too large %d", __func__, imm);
+    ASSERT_MSG(IsInRangeImm19(imm), "{}: offset too large {}", __func__, imm);
 
     Rt = DecodeReg(Rt);
     if (b64Bit && bitop != 0x2) // LDRSW(0x2) uses 64bit reg, doesn't have 64bit bit set
         bitop |= 0x1;
-    Write32((bitop << 30) | (bVec << 26) | (0x18 << 24) | (imm << 5) | Rt);
+    Write32((bitop << 30) | (bVec << 26) | (0x18 << 24) | (MaskImm19(imm) << 5) | Rt);
 }
 
 void ARM64XEmitter::EncodeLoadStoreExcInst(u32 instenc, ARM64Reg Rs, ARM64Reg Rt2, ARM64Reg Rn,
@@ -1510,13 +1510,13 @@ void ARM64XEmitter::UXTH(ARM64Reg Rd, ARM64Reg Rn) {
 }
 
 // Load Register (Literal)
-void ARM64XEmitter::LDR(ARM64Reg Rt, u32 imm) {
+void ARM64XEmitter::LDR(ARM64Reg Rt, s32 imm) {
     EncodeLoadRegisterInst(0, Rt, imm);
 }
-void ARM64XEmitter::LDRSW(ARM64Reg Rt, u32 imm) {
+void ARM64XEmitter::LDRSW(ARM64Reg Rt, s32 imm) {
     EncodeLoadRegisterInst(2, Rt, imm);
 }
-void ARM64XEmitter::PRFM(ARM64Reg Rt, u32 imm) {
+void ARM64XEmitter::PRFM(ARM64Reg Rt, s32 imm) {
     EncodeLoadRegisterInst(3, Rt, imm);
 }
 
diff --git a/src/backend/A64/emitter/a64_emitter.h b/src/backend/A64/emitter/a64_emitter.h
index 66a4303b..d5ea1b4d 100644
--- a/src/backend/A64/emitter/a64_emitter.h
+++ b/src/backend/A64/emitter/a64_emitter.h
@@ -475,7 +475,7 @@ private:
     void EncodeData2SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
     void EncodeData3SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
     void EncodeLogicalInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
-    void EncodeLoadRegisterInst(u32 bitop, ARM64Reg Rt, u32 imm);
+    void EncodeLoadRegisterInst(u32 bitop, ARM64Reg Rt, s32 imm);
     void EncodeLoadStoreExcInst(u32 instenc, ARM64Reg Rs, ARM64Reg Rt2, ARM64Reg Rn, ARM64Reg Rt);
     void EncodeLoadStorePairedInst(u32 op, ARM64Reg Rt, ARM64Reg Rt2, ARM64Reg Rn, u32 imm);
     void EncodeLoadStoreIndexedInst(u32 op, u32 op2, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
@@ -744,9 +744,9 @@ public:
     }
 
     // Load Register (Literal)
-    void LDR(ARM64Reg Rt, u32 imm);
-    void LDRSW(ARM64Reg Rt, u32 imm);
-    void PRFM(ARM64Reg Rt, u32 imm);
+    void LDR(ARM64Reg Rt, s32 imm);
+    void LDRSW(ARM64Reg Rt, s32 imm);
+    void PRFM(ARM64Reg Rt, s32 imm);
 
     // Load/Store Exclusive
     void STXRB(ARM64Reg Rs, ARM64Reg Rt, ARM64Reg Rn);