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backend\A64\emit_a64_packed.cpp: Implement Packed Select

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SachinVin 2019-07-27 13:33:54 +05:30 committed by xperia64
parent 01682cd735
commit ab27fbc0c6
3 changed files with 15 additions and 2 deletions
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13
src/backend/A64/emit_a64_packed.cpp
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@ -341,4 +341,17 @@ void EmitA64::EmitPackedSaturatedSubS16(EmitContext& ctx, IR::Inst* inst) {
code.fp_emitter.SQSUB(H, a, a, b); code.fp_emitter.SQSUB(H, a, a, b);
ctx.reg_alloc.DefineValue(inst, a); ctx.reg_alloc.DefineValue(inst, a);
} }
void EmitA64::EmitPackedSelect(EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
const ARM64Reg ge = EncodeRegToDouble(ctx.reg_alloc.UseScratchFpr(args[0]));
const ARM64Reg a = EncodeRegToDouble(ctx.reg_alloc.UseFpr(args[1]));
const ARM64Reg b = EncodeRegToDouble(ctx.reg_alloc.UseFpr(args[2]));
code.fp_emitter.BSL(ge, b, a);
ctx.reg_alloc.DefineValue(inst, ge);
}
} // namespace Dynarmic::BackendA64 } // namespace Dynarmic::BackendA64

2
src/backend/A64/opcodes.inc
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@ -213,7 +213,7 @@ OPCODE(PackedSaturatedAddS16, U32, U32,
OPCODE(PackedSaturatedSubU16, U32, U32, U32 ) OPCODE(PackedSaturatedSubU16, U32, U32, U32 )
OPCODE(PackedSaturatedSubS16, U32, U32, U32 ) OPCODE(PackedSaturatedSubS16, U32, U32, U32 )
//OPCODE(PackedAbsDiffSumS8, U32, U32, U32 ) //OPCODE(PackedAbsDiffSumS8, U32, U32, U32 )
//OPCODE(PackedSelect, U32, U32, U32, U32 ) OPCODE(PackedSelect, U32, U32, U32, U32 )
// CRC instructions // CRC instructions
//OPCODE(CRC32Castagnoli8, U32, U32, U32 ) //OPCODE(CRC32Castagnoli8, U32, U32, U32 )

2
src/frontend/A32/decoder/arm_a64.inc
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@ -182,7 +182,7 @@ INST(arm_MOVT, "MOVT", "cccc00110100vvvvddddvvvvvvvvvvvv
INST(arm_MOVW, "MOVW", "cccc00110000vvvvddddvvvvvvvvvvvv") // v6T2 INST(arm_MOVW, "MOVW", "cccc00110000vvvvddddvvvvvvvvvvvv") // v6T2
INST(arm_NOP, "NOP", "----0011001000001111000000000000") // v6K INST(arm_NOP, "NOP", "----0011001000001111000000000000") // v6K
INST(arm_SBFX, "SBFX", "cccc0111101wwwwwddddvvvvv101nnnn") // v6T2 INST(arm_SBFX, "SBFX", "cccc0111101wwwwwddddvvvvv101nnnn") // v6T2
//INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6 INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6
INST(arm_UBFX, "UBFX", "cccc0111111wwwwwddddvvvvv101nnnn") // v6T2 INST(arm_UBFX, "UBFX", "cccc0111111wwwwwddddvvvvv101nnnn") // v6T2
// Unsigned Sum of Absolute Differences instructions // Unsigned Sum of Absolute Differences instructions