diff --git a/src/frontend/A32/decoder/thumb32.h b/src/frontend/A32/decoder/thumb32.h index fe5464b6..15f0abc3 100644 --- a/src/frontend/A32/decoder/thumb32.h +++ b/src/frontend/A32/decoder/thumb32.h @@ -242,7 +242,7 @@ std::optional>> DecodeThumb32(u32 INST(&V::thumb32_SADD8, "SADD8", "111110101000nnnn1111dddd0000mmmm"), INST(&V::thumb32_SSUB8, "SSUB8", "111110101100nnnn1111dddd0000mmmm"), INST(&V::thumb32_QADD16, "QADD16", "111110101001nnnn1111dddd0001mmmm"), - //INST(&V::thumb32_QASX, "QASX", "111110101010----1111----0001----"), + INST(&V::thumb32_QASX, "QASX", "111110101010nnnn1111dddd0001mmmm"), //INST(&V::thumb32_QSAX, "QSAX", "111110101110----1111----0001----"), //INST(&V::thumb32_QSUB16, "QSUB16", "111110101101----1111----0001----"), //INST(&V::thumb32_QADD8, "QADD8", "111110101000----1111----0001----"), @@ -262,7 +262,7 @@ std::optional>> DecodeThumb32(u32 INST(&V::thumb32_UADD8, "UADD8", "111110101000nnnn1111dddd0100mmmm"), INST(&V::thumb32_USUB8, "USUB8", "111110101100nnnn1111dddd0100mmmm"), INST(&V::thumb32_UQADD16, "UQADD16", "111110101001nnnn1111dddd0101mmmm"), - //INST(&V::thumb32_UQASX, "UQASX", "111110101010----1111----0101----"), + INST(&V::thumb32_UQASX, "UQASX", "111110101010nnnn1111dddd0101mmmm"), //INST(&V::thumb32_UQSAX, "UQSAX", "111110101110----1111----0101----"), //INST(&V::thumb32_UQSUB16, "UQSUB16", "111110101101----1111----0101----"), //INST(&V::thumb32_UQADD8, "UQADD8", "111110101000----1111----0101----"), diff --git a/src/frontend/A32/translate/impl/thumb32_parallel.cpp b/src/frontend/A32/translate/impl/thumb32_parallel.cpp index 3e637d5c..1efbb22b 100644 --- a/src/frontend/A32/translate/impl/thumb32_parallel.cpp +++ b/src/frontend/A32/translate/impl/thumb32_parallel.cpp @@ -6,6 +6,13 @@ #include "frontend/A32/translate/impl/translate_thumb.h" namespace Dynarmic::A32 { +static IR::U32 Pack2x16To1x32(A32::IREmitter& ir, IR::U32 lo, IR::U32 hi) { + return ir.Or(ir.And(lo, ir.Imm32(0xFFFF)), ir.LogicalShiftLeft(hi, ir.Imm8(16), ir.Imm1(0)).result); +} + +static IR::U16 MostSignificantHalf(A32::IREmitter& ir, IR::U32 value) { + return ir.LeastSignificantHalf(ir.LogicalShiftRight(value, ir.Imm8(16), ir.Imm1(0)).result); +} bool ThumbTranslatorVisitor::thumb32_SADD8(Reg n, Reg d, Reg m) { if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { @@ -188,6 +195,25 @@ bool ThumbTranslatorVisitor::thumb32_QADD16(Reg n, Reg d, Reg m) { return true; } +bool ThumbTranslatorVisitor::thumb32_QASX(Reg n, Reg d, Reg m) { + if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { + return UnpredictableInstruction(); + } + + const auto Rn = ir.GetRegister(n); + const auto Rm = ir.GetRegister(m); + const auto Rn_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(Rn)); + const auto Rn_hi = ir.SignExtendHalfToWord(MostSignificantHalf(ir, Rn)); + const auto Rm_lo = ir.SignExtendHalfToWord(ir.LeastSignificantHalf(Rm)); + const auto Rm_hi = ir.SignExtendHalfToWord(MostSignificantHalf(ir, Rm)); + const auto diff = ir.SignedSaturation(ir.Sub(Rn_lo, Rm_hi), 16).result; + const auto sum = ir.SignedSaturation(ir.Add(Rn_hi, Rm_lo), 16).result; + const auto result = Pack2x16To1x32(ir, diff, sum); + + ir.SetRegister(d, result); + return true; +} + bool ThumbTranslatorVisitor::thumb32_UQADD16(Reg n, Reg d, Reg m) { if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { return UnpredictableInstruction(); @@ -201,4 +227,23 @@ bool ThumbTranslatorVisitor::thumb32_UQADD16(Reg n, Reg d, Reg m) { return true; } +bool ThumbTranslatorVisitor::thumb32_UQASX(Reg n, Reg d, Reg m) { + if (d == Reg::PC || n == Reg::PC || m == Reg::PC) { + return UnpredictableInstruction(); + } + + const auto Rn = ir.GetRegister(n); + const auto Rm = ir.GetRegister(m); + const auto Rn_lo = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(Rn)); + const auto Rn_hi = ir.ZeroExtendHalfToWord(MostSignificantHalf(ir, Rn)); + const auto Rm_lo = ir.ZeroExtendHalfToWord(ir.LeastSignificantHalf(Rm)); + const auto Rm_hi = ir.ZeroExtendHalfToWord(MostSignificantHalf(ir, Rm)); + const auto diff = ir.UnsignedSaturation(ir.Sub(Rn_lo, Rm_hi), 16).result; + const auto sum = ir.UnsignedSaturation(ir.Add(Rn_hi, Rm_lo), 16).result; + const auto result = Pack2x16To1x32(ir, diff, sum); + + ir.SetRegister(d, result); + return true; +} + } // namespace Dynarmic::A32 diff --git a/src/frontend/A32/translate/impl/translate_thumb.h b/src/frontend/A32/translate/impl/translate_thumb.h index 22bb2b12..c5ea19dd 100644 --- a/src/frontend/A32/translate/impl/translate_thumb.h +++ b/src/frontend/A32/translate/impl/translate_thumb.h @@ -143,7 +143,9 @@ struct ThumbTranslatorVisitor final { bool thumb32_USUB16(Reg n, Reg d, Reg m); bool thumb32_QADD16(Reg n, Reg d, Reg m); + bool thumb32_QASX(Reg n, Reg d, Reg m); bool thumb32_UQADD16(Reg n, Reg d, Reg m); + bool thumb32_UQASX(Reg n, Reg d, Reg m); }; } // namespace Dynarmic::A32 diff --git a/tests/A32/fuzz_thumb.cpp b/tests/A32/fuzz_thumb.cpp index 12416a60..4ff5a482 100644 --- a/tests/A32/fuzz_thumb.cpp +++ b/tests/A32/fuzz_thumb.cpp @@ -380,6 +380,8 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") { three_reg_not_r15), ThumbInstGen("111110101001nnnn1111dddd0001mmmm", // QADD16 three_reg_not_r15), + ThumbInstGen("111110101010nnnn1111dddd0001mmmm", // QASX + three_reg_not_r15), ThumbInstGen("111110101000nnnn1111dddd1001mmmm", // QDADD three_reg_not_r15), ThumbInstGen("111110101000nnnn1111dddd1011mmmm", // QDSUB @@ -436,6 +438,8 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") { three_reg_not_r15), ThumbInstGen("111110101001nnnn1111dddd0101mmmm", // UQADD16 three_reg_not_r15), + ThumbInstGen("111110101010nnnn1111dddd0101mmmm", // UQASX + three_reg_not_r15), ThumbInstGen("111110101110nnnn1111dddd0100mmmm", // USAX three_reg_not_r15), ThumbInstGen("111110101100nnnn1111dddd0100mmmm", // USUB8