backend\A64\emit_a64_floating_point.cpp: part 1
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xperia64
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src/backend/A64/emit_a64_floating_point.cpp
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300
src/backend/A64/emit_a64_floating_point.cpp
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <optional>
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#include <type_traits>
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#include <utility>
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#include "backend/a64/abi.h"
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#include "backend/a64/block_of_code.h"
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#include "backend/a64/emit_a64.h"
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/fp/fpcr.h"
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#include "common/fp/fpsr.h"
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#include "common/fp/info.h"
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#include "common/fp/op.h"
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#include "common/fp/rounding_mode.h"
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#include "common/fp/util.h"
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#include "common/mp/cartesian_product.h"
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#include "common/mp/integer.h"
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#include "common/mp/list.h"
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#include "common/mp/lut.h"
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#include "common/mp/to_tuple.h"
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#include "common/mp/vlift.h"
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#include "common/mp/vllift.h"
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#include "frontend/ir/basic_block.h"
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#include "frontend/ir/microinstruction.h"
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#include "frontend/ir/opcodes.h"
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namespace Dynarmic::BackendA64 {
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namespace mp = Dynarmic::Common::mp;
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namespace {
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const ARM64Reg INVALID_REG = ARM64Reg(-1);
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constexpr u64 f16_negative_zero = 0x8000;
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constexpr u64 f16_non_sign_mask = 0x7fff;
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constexpr u64 f32_negative_zero = 0x80000000u;
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constexpr u64 f32_nan = 0x7fc00000u;
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constexpr u64 f32_non_sign_mask = 0x7fffffffu;
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constexpr u64 f32_smallest_normal = 0x00800000u;
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constexpr u64 f64_negative_zero = 0x8000000000000000u;
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constexpr u64 f64_nan = 0x7ff8000000000000u;
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constexpr u64 f64_non_sign_mask = 0x7fffffffffffffffu;
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constexpr u64 f64_smallest_normal = 0x0010000000000000u;
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constexpr u64 f64_penultimate_positive_denormal = 0x000ffffffffffffeu;
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constexpr u64 f64_max_s32 = 0x41dfffffffc00000u; // 2147483647 as a double
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constexpr u64 f64_min_u32 = 0x0000000000000000u; // 0 as a double
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constexpr u64 f64_max_u32 = 0x41efffffffe00000u; // 4294967295 as a double
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constexpr u64 f64_max_s64_lim = 0x43e0000000000000u; // 2^63 as a double (actual maximum unrepresentable)
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constexpr u64 f64_min_u64 = 0x0000000000000000u; // 0 as a double
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constexpr u64 f64_max_u64_lim = 0x43f0000000000000u; // 2^64 as a double (actual maximum unrepresentable)
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//template<size_t fsize, typename T>
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//T ChooseOnFsize([[maybe_unused]] T f32, [[maybe_unused]] T f64) {
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// static_assert(fsize == 32 || fsize == 64, "fsize must be either 32 or 64");
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//
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// if constexpr (fsize == 32) {
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// return f32;
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// } else {
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// return f64;
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// }
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//}
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//
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//#define FCODE(NAME) (code.*ChooseOnFsize<fsize>(&Xbyak::CodeGenerator::NAME##s, &Xbyak::CodeGenerator::NAME##d))
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Arm64Gen::RoundingMode ConvertRoundingModeToA64RoundingMode(FP::RoundingMode rounding_mode) {
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switch (rounding_mode) {
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case FP::RoundingMode::ToNearest_TieEven:
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return RoundingMode::ROUND_N;
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case FP::RoundingMode::TowardsPlusInfinity:
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return RoundingMode::ROUND_P;
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case FP::RoundingMode::TowardsMinusInfinity:
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return RoundingMode::ROUND_M;
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case FP::RoundingMode::TowardsZero:
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return RoundingMode::ROUND_Z;
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case FP::RoundingMode::ToNearest_TieAwayFromZero:
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return RoundingMode::ROUND_A;
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default:
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UNREACHABLE();
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}
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}
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//template<size_t fsize>
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//void DenormalsAreZero(BlockOfCode& code, ARM64Reg xmm_value, ARM64Reg gpr_scratch) {
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// Xbyak::Label end;
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//
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// if constexpr (fsize == 32) {
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// code.fp_emitter.FMOV(DecodeReg(gpr_scratch), xmm_value);
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// code.ANDI2R(DecodeReg(gpr_scratch), DecodeReg(gpr_scratch), u32(0x7FFFFFFF));
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// code.SUBI2R(DecodeReg(gpr_scratch), DecodeReg(gpr_scratch), u32(1));
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// code.CMPI2R(DecodeReg(gpr_scratch), DecodeReg(gpr_scratch), u32(0x007FFFFE));
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// } else {
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// auto mask = code.MConst(xword, f64_non_sign_mask);
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// mask.setBit(64);
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// auto penult_denormal = code.MConst(xword, f64_penultimate_positive_denormal);
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// penult_denormal.setBit(64);
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//
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// code.movq(gpr_scratch, xmm_value);
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// code.and_(gpr_scratch, mask);
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// code.sub(gpr_scratch, u32(1));
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// code.cmp(gpr_scratch, penult_denormal);
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// }
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//
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// // We need to report back whether we've found a denormal on input.
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// // SSE doesn't do this for us when SSE's DAZ is enabled.
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//
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// code.ja(end);
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// code.andps(xmm_value, code.MConst(xword, fsize == 32 ? f32_negative_zero : f64_negative_zero));
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// code.mov(dword[r15 + code.GetJitStateInfo().offsetof_FPSCR_IDC], u32(1 << 7));
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// code.L(end);
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//}
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//
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//template<size_t fsize>
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//void ZeroIfNaN(BlockOfCode& code, ARM64Reg xmm_value, ARM64Reg xmm_scratch) {
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// code.xorps(xmm_scratch, xmm_scratch);
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// FCODE(cmpords)(xmm_scratch, xmm_value); // true mask when ordered (i.e.: when not an NaN)
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// code.pand(xmm_value, xmm_scratch);
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//}
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//template<size_t fsize>
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//void ForceToDefaultNaN(BlockOfCode& code, ARM64Reg result) {
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// FixupBranch end;
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//
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// code.fp_emitter.FCMP(result);
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// end = code.B(CC_VC);
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// code.LDR(result, code.MConst(fsize == 32 ? f32_nan : f64_nan));
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// code.SetJumpTarget(end);
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//}
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//template<size_t fsize>
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//FixupBranch ProcessNaN(BlockOfCode& code, ARM64Reg a, ARM64Reg scratch) {
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// FixupBranch not_nan, end;
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//
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// code.fp_emitter.FCMP(a);
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// not_nan = code.B(CC_VC);
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//
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// //code.SwitchToFarCode();
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// //code.SetJumpTarget(nan);
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//
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// code.EmitPatchLDR(scratch, fsize == 32 ? 0x00400000 : 0x0008'0000'0000'0000);
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// code.fp_emitter.ORR(EncodeRegToDouble(a), a, scratch);
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//
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// end = code.B();
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//
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// //code.FlushIcache();
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// //code.SwitchToNearCode();
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// code.SetJumpTarget(not_nan);
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// return end;
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//}
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//
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//template<size_t fsize>
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//void PostProcessNaN(BlockOfCode& code, Xbyak::Xmm result, Xbyak::Xmm tmp) {
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// if constexpr (fsize == 32) {
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// code.movaps(tmp, result);
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// code.cmpunordps(tmp, tmp);
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// code.pslld(tmp, 31);
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// code.xorps(result, tmp);
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// }
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// else {
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// code.movaps(tmp, result);
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// code.cmpunordpd(tmp, tmp);
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// code.psllq(tmp, 63);
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// code.xorps(result, tmp);
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// }
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//}
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// This is necessary because x86 and ARM differ in they way they return NaNs from floating point operations
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//
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// ARM behaviour:
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// op1 op2 result
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// SNaN SNaN/QNaN op1
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// QNaN SNaN op2
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// QNaN QNaN op1
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// SNaN/QNaN other op1
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// other SNaN/QNaN op2
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//
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// x86 behaviour:
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// op1 op2 result
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// SNaN/QNaN SNaN/QNaN op1
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// SNaN/QNaN other op1
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// other SNaN/QNaN op2
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//
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// With ARM: SNaNs take priority. With x86: it doesn't matter.
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//
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// From the above we can see what differs between the architectures is
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// the case when op1 == QNaN and op2 == SNaN.
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//
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// We assume that registers op1 and op2 are read-only. This function also trashes xmm0.
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// We allow for the case where op1 and result are the same register. We do not read from op1 once result is written to.
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//template<size_t fsize>
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//void EmitPostProcessNaNs(BlockOfCode& code, ARM64Reg result, ARM64Reg op1, ARM64Reg op2, Xbyak::Reg64 tmp, Xbyak::Label end) {
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// using FPT = mp::unsigned_integer_of_size<fsize>;
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// constexpr FPT exponent_mask = FP::FPInfo<FPT>::exponent_mask;
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// constexpr FPT mantissa_msb = FP::FPInfo<FPT>::mantissa_msb;
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// constexpr u8 mantissa_msb_bit = static_cast<u8>(FP::FPInfo<FPT>::explicit_mantissa_width - 1);
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//
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// // At this point we know that at least one of op1 and op2 is a NaN.
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// // Thus in op1 ^ op2 at least one of the two would have all 1 bits in the exponent.
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// // Keeping in mind xor is commutative, there are only four cases:
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// // SNaN ^ SNaN/Inf -> exponent == 0, mantissa_msb == 0
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// // QNaN ^ QNaN -> exponent == 0, mantissa_msb == 0
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// // QNaN ^ SNaN/Inf -> exponent == 0, mantissa_msb == 1
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// // SNaN/QNaN ^ Otherwise -> exponent != 0, mantissa_msb == ?
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// //
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// // We're only really interested in op1 == QNaN and op2 == SNaN,
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// // so we filter out everything else.
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// //
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// // We do it this way instead of checking that op1 is QNaN because
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// // op1 == QNaN && op2 == QNaN is the most common case. With this method
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// // that case would only require one branch.
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//
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// if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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// code.vxorps(xmm0, op1, op2);
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// } else {
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// code.movaps(xmm0, op1);
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// code.xorps(xmm0, op2);
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// }
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//
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// constexpr size_t shift = fsize == 32 ? 0 : 48;
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// if constexpr (fsize == 32) {
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// code.movd(tmp.cvt32(), xmm0);
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// } else {
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// // We do this to avoid requiring 64-bit immediates
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// code.pextrw(tmp.cvt32(), xmm0, shift / 16);
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// }
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// code.and_(tmp.cvt32(), static_cast<u32>((exponent_mask | mantissa_msb) >> shift));
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// code.cmp(tmp.cvt32(), static_cast<u32>(mantissa_msb >> shift));
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// code.jne(end, code.T_NEAR);
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//
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// // If we're here there are four cases left:
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// // op1 == SNaN && op2 == QNaN
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// // op1 == Inf && op2 == QNaN
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// // op1 == QNaN && op2 == SNaN <<< The problematic case
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// // op1 == QNaN && op2 == Inf
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//
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// if constexpr (fsize == 32) {
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// code.movd(tmp.cvt32(), op2);
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// code.shl(tmp.cvt32(), 32 - mantissa_msb_bit);
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// } else {
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// code.movq(tmp, op2);
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// code.shl(tmp, 64 - mantissa_msb_bit);
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// }
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// // If op2 is a SNaN, CF = 0 and ZF = 0.
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// code.jna(end, code.T_NEAR);
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//
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// // Silence the SNaN as required by spec.
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// if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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// code.vorps(result, op2, code.MConst(xword, mantissa_msb));
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// } else {
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// code.movaps(result, op2);
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// code.orps(result, code.MConst(xword, mantissa_msb));
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// }
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// code.jmp(end, code.T_NEAR);
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//}
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template <size_t fsize, typename Function>
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void FPTwoOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ARM64Reg result = ctx.reg_alloc.UseScratchFpr(args[0]);
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result = fsize == 32 ? EncodeRegToSingle(result) : EncodeRegToDouble(result);
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if constexpr (std::is_member_function_pointer_v<Function>) {
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(code.fp_emitter.*fn)(result, result);
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} else {
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fn(result);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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template <size_t fsize, typename Function>
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void FPThreeOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ARM64Reg result = ctx.reg_alloc.UseScratchFpr(args[0]);
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ARM64Reg operand = ctx.reg_alloc.UseScratchFpr(args[1]);
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result = fsize == 32 ? EncodeRegToSingle(result) : EncodeRegToDouble(result);
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operand = fsize == 32 ? EncodeRegToSingle(operand) : EncodeRegToDouble(operand);
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if constexpr (std::is_member_function_pointer_v<Function>) {
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(code.fp_emitter.*fn)(result, result, operand);
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}
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else {
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fn(result, result, operand);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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} // anonymous namespace
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} // namespace Dynarmic::BackendX64
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