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backend\A64: remove unused insructions

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This commit is contained in:
SachinVin 2022-05-28 17:41:32 +05:30
parent c654544aeb
commit b93759f914
2 changed files with 0 additions and 35 deletions
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32
src/dynarmic/backend/A64/a32_emit_a64.cpp
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@ -500,13 +500,6 @@ void A32EmitA64::EmitA32SetCpsrNZCVQ(A32EmitContext& ctx, IR::Inst* inst) {
code._MSR(FIELD_FPSR, host_fpsr);
}
void A32EmitA64::EmitA32GetNFlag(A32EmitContext& ctx, IR::Inst* inst) {
Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.ScratchGpr());
code.LDR(INDEX_UNSIGNED, result, X28, offsetof(A32JitState, cpsr_nzcv));
code.UBFX(result, result, 31, 1);
ctx.reg_alloc.DefineValue(inst, result);
}
void A32EmitA64::EmitA32SetNFlag(A32EmitContext& ctx, IR::Inst* inst) {
constexpr size_t flag_bit = 31;
constexpr u32 flag_mask = 1u << flag_bit;
@ -528,13 +521,6 @@ void A32EmitA64::EmitA32SetNFlag(A32EmitContext& ctx, IR::Inst* inst) {
code.STR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
}
void A32EmitA64::EmitA32GetZFlag(A32EmitContext& ctx, IR::Inst* inst) {
Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.ScratchGpr());
code.LDR(INDEX_UNSIGNED, result, X28, offsetof(A32JitState, cpsr_nzcv));
code.UBFX(result, result, 30, 1);
ctx.reg_alloc.DefineValue(inst, result);
}
void A32EmitA64::EmitA32SetZFlag(A32EmitContext& ctx, IR::Inst* inst) {
constexpr size_t flag_bit = 30;
constexpr u32 flag_mask = 1u << flag_bit;
@ -589,13 +575,6 @@ void A32EmitA64::EmitA32SetCFlag(A32EmitContext& ctx, IR::Inst* inst) {
code.STR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
}
void A32EmitA64::EmitA32GetVFlag(A32EmitContext& ctx, IR::Inst* inst) {
Arm64Gen::ARM64Reg result = DecodeReg(ctx.reg_alloc.ScratchGpr());
code.LDR(INDEX_UNSIGNED, result, X28, offsetof(A32JitState, cpsr_nzcv));
code.UBFX(result, result, 28, 1);
ctx.reg_alloc.DefineValue(inst, result);
}
void A32EmitA64::EmitA32SetVFlag(A32EmitContext& ctx, IR::Inst* inst) {
constexpr size_t flag_bit = 28;
constexpr u32 flag_mask = 1u << flag_bit;
@ -808,17 +787,6 @@ void A32EmitA64::EmitA32ClearExclusive(A32EmitContext&, IR::Inst*) {
code.STR(INDEX_UNSIGNED, WZR, X28, offsetof(A32JitState, exclusive_state));
}
void A32EmitA64::EmitA32SetExclusive(A32EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
ASSERT(args[1].IsImmediate());
Arm64Gen::ARM64Reg address = DecodeReg(ctx.reg_alloc.UseGpr(args[0]));
Arm64Gen::ARM64Reg state = DecodeReg(ctx.reg_alloc.ScratchGpr());
code.MOVI2R(state, u8(1));
code.STR(INDEX_UNSIGNED, state, X28, offsetof(A32JitState, exclusive_state));
code.STR(INDEX_UNSIGNED, address, X28, offsetof(A32JitState, exclusive_address));
}
A32EmitA64::DoNotFastmemMarker A32EmitA64::GenerateDoNotFastmemMarker(A32EmitContext& ctx, IR::Inst* inst) {
return std::make_tuple(ctx.Location(), ctx.GetInstOffset(inst));
}

3
src/dynarmic/backend/A64/opcodes.inc
View File

@ -22,13 +22,10 @@ A32OPC(SetCpsr, Void, U32
A32OPC(SetCpsrNZCV, Void, NZCV )
A32OPC(SetCpsrNZCVRaw, Void, U32 )
A32OPC(SetCpsrNZCVQ, Void, U32 )
A32OPC(GetNFlag, U1, )
A32OPC(SetNFlag, Void, U1 )
A32OPC(GetZFlag, U1, )
A32OPC(SetZFlag, Void, U1 )
A32OPC(GetCFlag, U1, )
A32OPC(SetCFlag, Void, U1 )
A32OPC(GetVFlag, U1, )
A32OPC(SetVFlag, Void, U1 )
A32OPC(OrQFlag, Void, U1 )
A32OPC(GetGEFlags, U32, )