a64 backend: Load "guest_FPSR"
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@ -146,20 +146,17 @@ void A32JitState::SetFpscr(u32 FPSCR) {
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FPSCR_mode = FPSCR & FPSCR_MODE_MASK;
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FPSCR_nzcv = FPSCR & FPSCR_NZCV_MASK;
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guest_FPCR = 0;
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// RMode
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guest_FPCR |= FPSCR & 0xC00000;
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guest_FPSR = 0;
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// Cumulative flags IDC, IOC, IXC, UFC, OFC, DZC
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FPSCR_IDC = 0;
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FPSCR_UFC = 0;
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fpsr_exc = FPSCR & 0x9F;
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if (Common::Bit<24>(FPSCR)) {
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// VFP Flush to Zero
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//guest_MXCSR |= (1 << 15); // SSE Flush to Zero
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//guest_MXCSR |= (1 << 6); // SSE Denormals are Zero
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}
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// Mode Bits
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guest_FPCR |= FPSCR & 0x07C09F00;
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// Exceptions
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guest_FPSR |= FPSCR & 0x9F;
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}
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u64 A32JitState::GetUniqueHash() const {
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@ -226,13 +226,19 @@ void BlockOfCode::GenRunCode() {
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void BlockOfCode::SwitchMxcsrOnEntry() {
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MRS(ABI_SCRATCH1, Arm64Gen::FIELD_FPCR);
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STR(Arm64Gen::INDEX_UNSIGNED, ABI_SCRATCH1, Arm64Gen::X28, jsi.offsetof_save_host_FPCR);
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LDR(Arm64Gen::INDEX_UNSIGNED, ABI_SCRATCH1, Arm64Gen::X28, jsi.offsetof_guest_FPCR);
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_MSR(Arm64Gen::FIELD_FPCR, ABI_SCRATCH1);
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LDR(Arm64Gen::INDEX_UNSIGNED, ABI_SCRATCH1, Arm64Gen::X28, jsi.offsetof_guest_FPSR);
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_MSR(Arm64Gen::FIELD_FPSR, ABI_SCRATCH1);
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}
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void BlockOfCode::SwitchMxcsrOnExit() {
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MRS(ABI_SCRATCH1, Arm64Gen::FIELD_FPCR);
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STR(Arm64Gen::INDEX_UNSIGNED, ABI_SCRATCH1, Arm64Gen::X28, jsi.offsetof_guest_FPCR);
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MRS(ABI_SCRATCH1, Arm64Gen::FIELD_FPSR);
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STR(Arm64Gen::INDEX_UNSIGNED, ABI_SCRATCH1, Arm64Gen::X28, jsi.offsetof_guest_FPSR);
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LDR(Arm64Gen::INDEX_UNSIGNED, ABI_SCRATCH1, Arm64Gen::X28, jsi.offsetof_save_host_FPCR);
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_MSR(Arm64Gen::FIELD_FPCR, ABI_SCRATCH1);
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}
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