diff --git a/src/backend/x64/emit_x64_vector_floating_point.cpp b/src/backend/x64/emit_x64_vector_floating_point.cpp
index a9b85a7f..e7bb67c5 100644
--- a/src/backend/x64/emit_x64_vector_floating_point.cpp
+++ b/src/backend/x64/emit_x64_vector_floating_point.cpp
@@ -1092,6 +1092,10 @@ static void EmitRecipEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* ins
     });
 }
 
+void EmitX64::EmitFPVectorRecipEstimate16(EmitContext& ctx, IR::Inst* inst) {
+    EmitRecipEstimate<u16>(code, ctx, inst);
+}
+
 void EmitX64::EmitFPVectorRecipEstimate32(EmitContext& ctx, IR::Inst* inst) {
     EmitRecipEstimate<u32>(code, ctx, inst);
 }
diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp
index a421ff29..b100fc67 100644
--- a/src/frontend/ir/ir_emitter.cpp
+++ b/src/frontend/ir/ir_emitter.cpp
@@ -2273,6 +2273,8 @@ U128 IREmitter::FPVectorPairedAddLower(size_t esize, const U128& a, const U128&
 
 U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a) {
     switch (esize) {
+    case 16:
+        return Inst<U128>(Opcode::FPVectorRecipEstimate16, a);
     case 32:
         return Inst<U128>(Opcode::FPVectorRecipEstimate32, a);
     case 64:
diff --git a/src/frontend/ir/microinstruction.cpp b/src/frontend/ir/microinstruction.cpp
index 8a2d49d8..1ca31446 100644
--- a/src/frontend/ir/microinstruction.cpp
+++ b/src/frontend/ir/microinstruction.cpp
@@ -337,6 +337,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
     case Opcode::FPVectorPairedAddLower64:
     case Opcode::FPVectorPairedAdd32:
     case Opcode::FPVectorPairedAdd64:
+    case Opcode::FPVectorRecipEstimate16:
     case Opcode::FPVectorRecipEstimate32:
     case Opcode::FPVectorRecipEstimate64:
     case Opcode::FPVectorRecipStepFused16:
diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc
index 07fe9ca4..36bf30f6 100644
--- a/src/frontend/ir/opcodes.inc
+++ b/src/frontend/ir/opcodes.inc
@@ -572,6 +572,7 @@ OPCODE(FPVectorPairedAdd32,                                 U128,           U128
 OPCODE(FPVectorPairedAdd64,                                 U128,           U128,           U128                                            )
 OPCODE(FPVectorPairedAddLower32,                            U128,           U128,           U128                                            )
 OPCODE(FPVectorPairedAddLower64,                            U128,           U128,           U128                                            )
+OPCODE(FPVectorRecipEstimate16,                             U128,           U128                                                            )
 OPCODE(FPVectorRecipEstimate32,                             U128,           U128                                                            )
 OPCODE(FPVectorRecipEstimate64,                             U128,           U128                                                            )
 OPCODE(FPVectorRecipStepFused16,                            U128,           U128,           U128                                            )