diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 50a577a2..fd016185 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -652,7 +652,7 @@ INST(FCMLE_4, "FCMLE (zero)", "0Q101 INST(FCVTPU_4, "FCVTPU (vector)", "0Q1011101z100001101010nnnnnddddd") //INST(FCVTZU_int_3, "FCVTZU (vector, integer)", "0Q10111011111001101110nnnnnddddd") INST(FCVTZU_int_4, "FCVTZU (vector, integer)", "0Q1011101z100001101110nnnnnddddd") -//INST(URSQRTE, "URSQRTE", "0Q1011101z100001110010nnnnnddddd") +INST(URSQRTE, "URSQRTE", "0Q1011101z100001110010nnnnnddddd") //INST(FRSQRTE_3, "FRSQRTE", "0Q10111011111001110110nnnnnddddd") INST(FRSQRTE_4, "FRSQRTE", "0Q1011101z100001110110nnnnnddddd") //INST(FSQRT_1, "FSQRT (vector)", "0Q10111011111001111110nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp index f103ce16..6218dc30 100644 --- a/src/frontend/A64/translate/impl/simd_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_two_register_misc.cpp @@ -659,6 +659,20 @@ bool TranslatorVisitor::URECPE(bool Q, bool sz, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::URSQRTE(bool Q, bool sz, Vec Vn, Vec Vd) { + if (sz) { + return ReservedValue(); + } + + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand = V(datasize, Vn); + const IR::U128 result = ir.VectorUnsignedRecipSqrtEstimate(operand); + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) { return IntegerConvertToFloat(*this, Q, sz, Vn, Vd, Signedness::Signed); }