From d9f803924e5a6d42c0524e40ee7429cd3cd38f6d Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sat, 10 Feb 2018 11:25:50 +0000 Subject: [PATCH] IR: Implement VectorSub --- src/backend_x64/emit_x64_vector.cpp | 16 ++++++++++++++++ src/frontend/ir/ir_emitter.cpp | 15 +++++++++++++++ src/frontend/ir/ir_emitter.h | 1 + src/frontend/ir/opcodes.inc | 4 ++++ 4 files changed, 36 insertions(+) diff --git a/src/backend_x64/emit_x64_vector.cpp b/src/backend_x64/emit_x64_vector.cpp index 45974313..7c206005 100644 --- a/src/backend_x64/emit_x64_vector.cpp +++ b/src/backend_x64/emit_x64_vector.cpp @@ -687,6 +687,22 @@ void EmitX64::EmitVectorLogicalShiftRight64(EmitContext& ctx, IR::Inst* inst) { ctx.reg_alloc.DefineValue(inst, result); } +void EmitX64::EmitVectorSub8(EmitContext& ctx, IR::Inst* inst) { + EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::psubb); +} + +void EmitX64::EmitVectorSub16(EmitContext& ctx, IR::Inst* inst) { + EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::psubw); +} + +void EmitX64::EmitVectorSub32(EmitContext& ctx, IR::Inst* inst) { + EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::psubd); +} + +void EmitX64::EmitVectorSub64(EmitContext& ctx, IR::Inst* inst) { + EmitVectorOperation(code, ctx, inst, &Xbyak::CodeGenerator::psubq); +} + static void EmitVectorZeroExtend(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, int size) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index 34837302..5681e1b3 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -934,6 +934,21 @@ U128 IREmitter::VectorPairedAdd(size_t esize, const U128& a, const U128& b) { return {}; } +U128 IREmitter::VectorSub(size_t esize, const U128& a, const U128& b) { + switch (esize) { + case 8: + return Inst(Opcode::VectorSub8, a, b); + case 16: + return Inst(Opcode::VectorSub16, a, b); + case 32: + return Inst(Opcode::VectorSub32, a, b); + case 64: + return Inst(Opcode::VectorSub64, a, b); + } + UNREACHABLE(); + return {}; +} + U128 IREmitter::VectorZeroExtend(size_t original_esize, const U128& a) { switch (original_esize) { case 8: diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index da536852..01928f57 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -220,6 +220,7 @@ public: U128 VectorOr(const U128& a, const U128& b); U128 VectorPairedAdd(size_t esize, const U128& a, const U128& b); U128 VectorPairedAddLower(size_t esize, const U128& a, const U128& b); + U128 VectorSub(size_t esize, const U128& a, const U128& b); U128 VectorZeroExtend(size_t original_esize, const U128& a); U128 VectorZeroUpper(const U128& a); diff --git a/src/frontend/ir/opcodes.inc b/src/frontend/ir/opcodes.inc index 668a6bef..4d1049b7 100644 --- a/src/frontend/ir/opcodes.inc +++ b/src/frontend/ir/opcodes.inc @@ -237,6 +237,10 @@ OPCODE(VectorPairedAdd8, T::U128, T::U128, T::U128 OPCODE(VectorPairedAdd16, T::U128, T::U128, T::U128 ) OPCODE(VectorPairedAdd32, T::U128, T::U128, T::U128 ) OPCODE(VectorPairedAdd64, T::U128, T::U128, T::U128 ) +OPCODE(VectorSub8, T::U128, T::U128, T::U128 ) +OPCODE(VectorSub16, T::U128, T::U128, T::U128 ) +OPCODE(VectorSub32, T::U128, T::U128, T::U128 ) +OPCODE(VectorSub64, T::U128, T::U128, T::U128 ) OPCODE(VectorZeroExtend8, T::U128, T::U128 ) OPCODE(VectorZeroExtend16, T::U128, T::U128 ) OPCODE(VectorZeroExtend32, T::U128, T::U128 )