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simd_two_register_misc: Handle 64-bit case for SCVTF_int_4

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Lioncash 2018-05-08 11:53:59 -04:00 committed by Merry
parent b166981ff5
commit e0faf3277e
1 changed files with 1 additions and 6 deletions
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7
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
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@ -267,15 +267,10 @@ bool TranslatorVisitor::SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
return ReservedValue();
}
if (sz) {
// TODO: Implement
return InterpretThisInstruction();
}
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 result = ir.FPVectorS32ToSingle(operand);
const IR::U128 result = sz ? ir.FPVectorS64ToDouble(operand) : ir.FPVectorS32ToSingle(operand);
V(datasize, Vd, result);
return true;