simd_two_register_misc: Handle 64-bit case for SCVTF_int_4
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@ -267,15 +267,10 @@ bool TranslatorVisitor::SCVTF_int_4(bool Q, bool sz, Vec Vn, Vec Vd) {
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return ReservedValue();
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return ReservedValue();
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}
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}
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if (sz) {
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// TODO: Implement
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return InterpretThisInstruction();
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}
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const size_t datasize = Q ? 128 : 64;
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const size_t datasize = Q ? 128 : 64;
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const IR::U128 operand = V(datasize, Vn);
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const IR::U128 operand = V(datasize, Vn);
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const IR::U128 result = ir.FPVectorS32ToSingle(operand);
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const IR::U128 result = sz ? ir.FPVectorS64ToDouble(operand) : ir.FPVectorS32ToSingle(operand);
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V(datasize, Vd, result);
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V(datasize, Vd, result);
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return true;
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return true;
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