From e71e560673a325532c58a5a4e22227aa7de590c0 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Fri, 1 Mar 2019 00:58:47 -0500
Subject: [PATCH] translate_arm/misc: Invert conditionals where applicable

---
 .../A32/translate/translate_arm/misc.cpp      | 29 ++++++++++++-------
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/src/frontend/A32/translate/translate_arm/misc.cpp b/src/frontend/A32/translate/translate_arm/misc.cpp
index 9624b1e4..100c1271 100644
--- a/src/frontend/A32/translate/translate_arm/misc.cpp
+++ b/src/frontend/A32/translate/translate_arm/misc.cpp
@@ -8,26 +8,35 @@
 
 namespace Dynarmic::A32 {
 
+// CLZ<c> <Rd>, <Rm>
 bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
-    if (d == Reg::PC || m == Reg::PC)
+    if (d == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
-    if (ConditionPassed(cond)) {
-        ir.SetRegister(d, ir.CountLeadingZeros(ir.GetRegister(m)));
     }
+
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    ir.SetRegister(d, ir.CountLeadingZeros(ir.GetRegister(m)));
     return true;
 }
 
+// SEL<c> <Rd>, <Rn>, <Rm>
 bool ArmTranslatorVisitor::arm_SEL(Cond cond, Reg n, Reg d, Reg m) {
-    if (n == Reg::PC || d == Reg::PC || m == Reg::PC)
+    if (n == Reg::PC || d == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
-
-    if (ConditionPassed(cond)) {
-        auto to = ir.GetRegister(m);
-        auto from = ir.GetRegister(n);
-        auto result = ir.PackedSelect(ir.GetGEFlags(), to, from);
-        ir.SetRegister(d, result);
     }
 
+    if (!ConditionPassed(cond)) {
+        return true;
+    }
+
+    const auto to = ir.GetRegister(m);
+    const auto from = ir.GetRegister(n);
+    const auto result = ir.PackedSelect(ir.GetGEFlags(), to, from);
+
+    ir.SetRegister(d, result);
     return true;
 }