backend\A64\emit_a64_data_processing.cpp: Implement Arithmetic ops
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SachinVin
xperia64
parent
361d221741
commit
ea54d71e3b
@ -717,4 +717,191 @@ void EmitA64::EmitRotateRightExtended(EmitContext& ctx, IR::Inst* inst) {
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ctx.reg_alloc.DefineValue(inst, result);
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}
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static Arm64Gen::ARM64Reg DoCarry(RegAlloc& reg_alloc, Argument& carry_in, IR::Inst* carry_out) {
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if (carry_in.IsImmediate()) {
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return carry_out ? reg_alloc.ScratchGpr() : INVALID_REG;
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} else {
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return carry_out ? reg_alloc.UseScratchGpr(carry_in) : reg_alloc.UseGpr(carry_in);
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}
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}
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static Arm64Gen::ARM64Reg DoNZCV(BlockOfCode& code, RegAlloc& reg_alloc, IR::Inst* nzcv_out) {
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if (!nzcv_out)
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return INVALID_REG;
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Arm64Gen::ARM64Reg nzcv = reg_alloc.ScratchGpr();
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code.MOVI2R(nzcv, 0);
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return nzcv;
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}
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static void EmitAdd(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, int bitsize) {
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auto carry_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp);
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auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
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auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto& carry_in = args[2];
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Arm64Gen::ARM64Reg nzcv = DoNZCV(code, ctx.reg_alloc, nzcv_inst);
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Arm64Gen::ARM64Reg result = ctx.reg_alloc.UseScratchGpr(args[0]);
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Arm64Gen::ARM64Reg carry = DecodeReg(DoCarry(ctx.reg_alloc, carry_in, carry_inst));
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Arm64Gen::ARM64Reg overflow = overflow_inst ? ctx.reg_alloc.ScratchGpr() : INVALID_REG;
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result = bitsize == 64 ? result : DecodeReg(result);
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if (args[1].IsImmediate() && args[1].GetType() == IR::Type::U32) {
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if (carry_in.IsImmediate()) {
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if (carry_in.GetImmediateU1()) {
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Arm64Gen::ARM64Reg op_arg = ctx.reg_alloc.UseGpr(args[1]);
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code.CMP(op_arg, op_arg);
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code.ADCS(result, result, op_arg);
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} else {
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u32 op_arg = args[1].GetImmediateU32();
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code.ADDSI2R(result, result, op_arg, code.ABI_SCRATCH1);
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}
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} else {
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Arm64Gen::ARM64Reg op_arg = ctx.reg_alloc.UseGpr(args[1]);
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code.CMPI2R(carry, 1);
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code.ADCS(result, result, op_arg);
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}
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} else {
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Arm64Gen::ARM64Reg op_arg = ctx.reg_alloc.UseGpr(args[1]);
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if (carry_in.IsImmediate()) {
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if (carry_in.GetImmediateU1()) {
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code.CMP(DecodeReg(op_arg), DecodeReg(op_arg));
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code.ADCS(result, result, op_arg);
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} else {
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code.ADDS(result,result, op_arg);
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}
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} else {
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code.CMPI2R(DecodeReg(carry), 1);
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code.ADCS(result, result, op_arg);
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}
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}
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if (nzcv_inst) {
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code.MRS(nzcv, FIELD_NZCV);
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ctx.reg_alloc.DefineValue(nzcv_inst, nzcv);
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ctx.EraseInstruction(nzcv_inst);
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}
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if (carry_inst) {
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code.CSET(carry, CC_CS);
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ctx.reg_alloc.DefineValue(carry_inst, carry);
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ctx.EraseInstruction(carry_inst);
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}
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if (overflow_inst) {
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code.CSET(overflow, CC_VS);
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ctx.reg_alloc.DefineValue(overflow_inst, overflow);
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ctx.EraseInstruction(overflow_inst);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitAdd32(EmitContext& ctx, IR::Inst* inst) {
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EmitAdd(code, ctx, inst, 32);
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}
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void EmitA64::EmitAdd64(EmitContext& ctx, IR::Inst* inst) {
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EmitAdd(code, ctx, inst, 64);
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}
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static void EmitSub(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, int bitsize) {
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auto carry_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp);
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auto overflow_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp);
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auto nzcv_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetNZCVFromOp);
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto& carry_in = args[2];
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Arm64Gen::ARM64Reg nzcv = DoNZCV(code, ctx.reg_alloc, nzcv_inst);
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Arm64Gen::ARM64Reg result = ctx.reg_alloc.UseScratchGpr(args[0]);
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Arm64Gen::ARM64Reg carry = DoCarry(ctx.reg_alloc, carry_in, carry_inst);
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Arm64Gen::ARM64Reg overflow = overflow_inst ? ctx.reg_alloc.ScratchGpr() : INVALID_REG;
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// TODO: Consider using LEA.
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// TODO: Optimize CMP case.
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result = bitsize == 64 ? result : DecodeReg(result);
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if (args[1].IsImmediate() && args[1].GetType() == IR::Type::U32) {
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if (carry_in.IsImmediate()) {
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if (carry_in.GetImmediateU1()) {
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u32 op_arg = args[1].GetImmediateU32();
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code.SUBSI2R(result, result, op_arg, code.ABI_SCRATCH1);
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} else {
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Arm64Gen::ARM64Reg op_arg = ctx.reg_alloc.UseGpr(args[1]);
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code.ADDSI2R(op_arg, op_arg, 0); // Clear carry
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code.SBCS(result, result, op_arg);
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}
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} else {
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Arm64Gen::ARM64Reg op_arg = ctx.reg_alloc.UseGpr(args[1]);
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code.CMPI2R(carry, 0x1);
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code.SBCS(result, result, op_arg);
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}
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} else {
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Arm64Gen::ARM64Reg op_arg = ctx.reg_alloc.UseGpr(args[1]);
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if (carry_in.IsImmediate()) {
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if (carry_in.GetImmediateU1()) {
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code.SUBS(result, result, op_arg);
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} else {
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code.ADDSI2R(DecodeReg(op_arg), DecodeReg(op_arg), 0); // Clear carry
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code.SBCS(result,result, op_arg);
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}
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} else {
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code.CMPI2R(DecodeReg(carry), 0x1);
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code.SBCS(result,result, op_arg);
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}
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}
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if (nzcv_inst) {
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code.MRS(nzcv, FIELD_NZCV);
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ctx.reg_alloc.DefineValue(nzcv_inst, nzcv);
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ctx.EraseInstruction(nzcv_inst);
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}
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if (carry_inst) {
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code.CSET(carry, CC_CS);
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ctx.reg_alloc.DefineValue(carry_inst, carry);
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ctx.EraseInstruction(carry_inst);
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}
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if (overflow_inst) {
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code.CSET(overflow, CC_VS);
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ctx.reg_alloc.DefineValue(overflow_inst, overflow);
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ctx.EraseInstruction(overflow_inst);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitSub32(EmitContext& ctx, IR::Inst* inst) {
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EmitSub(code, ctx, inst, 32);
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}
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void EmitA64::EmitSub64(EmitContext& ctx, IR::Inst* inst) {
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EmitSub(code, ctx, inst, 64);
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}
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void EmitA64::EmitMul32(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ARM64Reg result = DecodeReg(ctx.reg_alloc.UseScratchGpr(args[0]));
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ARM64Reg op_arg = DecodeReg(ctx.reg_alloc.UseGpr(args[1]));
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code.MUL(result, result, op_arg);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitA64::EmitMul64(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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ARM64Reg result = ctx.reg_alloc.UseScratchGpr(args[0]);
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ARM64Reg op_arg = ctx.reg_alloc.UseGpr(args[1]);
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code.MUL(result, result, op_arg);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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} // namespace Dynarmic::BackendA64
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@ -108,13 +108,13 @@ OPCODE(ArithmeticShiftRight32, U32, U32,
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//OPCODE(ArithmeticShiftRight64, U64, U64, U8 )
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OPCODE(RotateRight32, U32, U32, U8, U1 )
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//OPCODE(RotateRight64, U64, U64, U8 )
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//OPCODE(Add32, U32, U32, U32, U1 )
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//OPCODE(Add64, U64, U64, U64, U1 )
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//OPCODE(Sub32, U32, U32, U32, U1 )
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//OPCODE(Sub64, U64, U64, U64, U1 )
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//OPCODE(Mul32, U32, U32, U32 )
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//OPCODE(Mul64, U64, U64, U64 )
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OPCODE(RotateRightExtended, U32, U32, U1 )
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OPCODE(Add32, U32, U32, U32, U1 )
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OPCODE(Add64, U64, U64, U64, U1 )
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OPCODE(Sub32, U32, U32, U32, U1 )
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OPCODE(Sub64, U64, U64, U64, U1 )
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OPCODE(Mul32, U32, U32, U32 )
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OPCODE(Mul64, U64, U64, U64 )
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//OPCODE(SignedMultiplyHigh64, U64, U64, U64 )
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//OPCODE(UnsignedMultiplyHigh64, U64, U64, U64 )
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//OPCODE(UnsignedDiv32, U32, U32, U32 )
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