diff --git a/src/dynarmic/backend/A64/a32_emit_a64.cpp b/src/dynarmic/backend/A64/a32_emit_a64.cpp
index 7ee06bae..ba684ce3 100644
--- a/src/dynarmic/backend/A64/a32_emit_a64.cpp
+++ b/src/dynarmic/backend/A64/a32_emit_a64.cpp
@@ -504,47 +504,7 @@ void A32EmitA64::EmitA32SetCpsrNZCVQ(A32EmitContext& ctx, IR::Inst* inst) {
     code._MSR(FIELD_FPSR, host_fpsr);
 }
 
-void A32EmitA64::EmitA32SetNFlag(A32EmitContext& ctx, IR::Inst* inst) {
-    constexpr size_t flag_bit = 31;
-    constexpr u32 flag_mask = 1u << flag_bit;
-    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    Arm64Gen::ARM64Reg nzcv = DecodeReg(ctx.reg_alloc.ScratchGpr());
 
-    code.LDR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
-    if (args[0].IsImmediate()) {
-        if (args[0].GetImmediateU1()) {
-            code.ORRI2R(nzcv, nzcv, flag_mask);
-        } else {
-            code.ANDI2R(nzcv, nzcv, ~flag_mask);
-        }
-    } else {
-        Arm64Gen::ARM64Reg to_store = DecodeReg(ctx.reg_alloc.UseGpr(args[0]));
-
-        code.BFI(nzcv, to_store, flag_bit, 1);
-    }
-    code.STR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
-}
-
-void A32EmitA64::EmitA32SetZFlag(A32EmitContext& ctx, IR::Inst* inst) {
-    constexpr size_t flag_bit = 30;
-    constexpr u32 flag_mask = 1u << flag_bit;
-    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    Arm64Gen::ARM64Reg nzcv = DecodeReg(ctx.reg_alloc.ScratchGpr());
-
-    code.LDR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
-    if (args[0].IsImmediate()) {
-        if (args[0].GetImmediateU1()) {
-            code.ORRI2R(nzcv, nzcv, flag_mask);
-        } else {
-            code.ANDI2R(nzcv, nzcv, ~flag_mask);
-        }
-    } else {
-        Arm64Gen::ARM64Reg to_store = DecodeReg(ctx.reg_alloc.UseScratchGpr(args[0]));
-
-        code.BFI(nzcv, to_store, flag_bit, 1);
-    }
-    code.STR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
-}
 
 void A32EmitA64::EmitA32SetCheckBit(A32EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
@@ -559,47 +519,6 @@ void A32EmitA64::EmitA32GetCFlag(A32EmitContext& ctx, IR::Inst* inst) {
     ctx.reg_alloc.DefineValue(inst, result);
 }
 
-void A32EmitA64::EmitA32SetCFlag(A32EmitContext& ctx, IR::Inst* inst) {
-    constexpr size_t flag_bit = 29;
-    constexpr u32 flag_mask = 1u << flag_bit;
-    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    Arm64Gen::ARM64Reg nzcv = DecodeReg(ctx.reg_alloc.ScratchGpr());
-
-    code.LDR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
-    if (args[0].IsImmediate()) {
-        if (args[0].GetImmediateU1()) {
-            code.ORRI2R(nzcv, nzcv, flag_mask);
-        } else {
-            code.ANDI2R(nzcv, nzcv, ~flag_mask);
-        }
-    } else {
-        Arm64Gen::ARM64Reg to_store = DecodeReg(ctx.reg_alloc.UseScratchGpr(args[0]));
-        code.BFI(nzcv, to_store, flag_bit, 1);
-    }
-    code.STR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
-}
-
-void A32EmitA64::EmitA32SetVFlag(A32EmitContext& ctx, IR::Inst* inst) {
-    constexpr size_t flag_bit = 28;
-    constexpr u32 flag_mask = 1u << flag_bit;
-    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    Arm64Gen::ARM64Reg nzcv = DecodeReg(ctx.reg_alloc.ScratchGpr());
-
-    code.LDR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
-    if (args[0].IsImmediate()) {
-        if (args[0].GetImmediateU1()) {
-            code.ORRI2R(nzcv, nzcv, flag_mask);
-        } else {
-            code.ANDI2R(nzcv, nzcv, ~flag_mask);
-        }
-    } else {
-        Arm64Gen::ARM64Reg to_store = DecodeReg(ctx.reg_alloc.UseGpr(args[0]));
-
-        code.BFI(nzcv, to_store, flag_bit, 1);
-    }
-    code.STR(INDEX_UNSIGNED, nzcv, X28, offsetof(A32JitState, cpsr_nzcv));
-}
-
 void A32EmitA64::EmitA32OrQFlag(A32EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
     if (args[0].IsImmediate()) {
diff --git a/src/dynarmic/backend/A64/opcodes.inc b/src/dynarmic/backend/A64/opcodes.inc
index b529d0fb..34933052 100644
--- a/src/dynarmic/backend/A64/opcodes.inc
+++ b/src/dynarmic/backend/A64/opcodes.inc
@@ -22,11 +22,7 @@ A32OPC(SetCpsr,                                             Void,           U32
 A32OPC(SetCpsrNZCV,                                         Void,           NZCV                                                            )
 A32OPC(SetCpsrNZCVRaw,                                      Void,           U32                                                             )
 A32OPC(SetCpsrNZCVQ,                                        Void,           U32                                                             )
-A32OPC(SetNFlag,                                            Void,           U1                                                              )
-A32OPC(SetZFlag,                                            Void,           U1                                                              )
 A32OPC(GetCFlag,                                            U1,                                                                             )
-A32OPC(SetCFlag,                                            Void,           U1                                                              )
-A32OPC(SetVFlag,                                            Void,           U1                                                              )
 A32OPC(OrQFlag,                                             Void,           U1                                                              )
 A32OPC(GetGEFlags,                                          U32,                                                                            )
 A32OPC(SetGEFlags,                                          Void,           U32                                                             )