From f6b665f5a4b2346058f00f21751fd97f977bba7a Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Wed, 17 Jun 2020 15:53:35 -0400
Subject: [PATCH] A32: Implement ASIMD VQABS
---
src/frontend/A32/decoder/asimd.inc | 2 +-
.../translate/impl/asimd_two_regs_misc.cpp | 20 +++++++++++++++++++
.../A32/translate/impl/translate_arm.h | 1 +
3 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc
index 307cb0a4..7ca90b68 100644
--- a/src/frontend/A32/decoder/asimd.inc
+++ b/src/frontend/A32/decoder/asimd.inc
@@ -83,7 +83,7 @@ INST(asimd_VCLZ, "VCLZ", "111100111D11zz00dddd010
INST(asimd_VCNT, "VCNT", "111100111D11zz00dddd01010QM0mmmm") // ASIMD
//INST(asimd_VMVN_reg, "VMVN_reg", "111100111-11--00----01011x-0----") // ASIMD
//INST(asimd_VPADAL, "VPADAL", "111100111-11--00----0110xx-0----") // ASIMD
-//INST(asimd_VQABS, "VQABS", "111100111-11--00----01110x-0----") // ASIMD
+INST(asimd_VQABS, "VQABS", "111100111D11zz00dddd01110QM0mmmm") // ASIMD
//INST(asimd_VQNEG, "VQNEG", "111100111-11--00----01111x-0----") // ASIMD
//INST(asimd_VCGT_zero, "VCGT (zero)", "111100111-11--01----0x000x-0----") // ASIMD
//INST(asimd_VCGE_zero, "VCGE (zero)", "111100111-11--01----0x001x-0----") // ASIMD
diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
index e1bad909..bc5fbee8 100644
--- a/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
+++ b/src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
@@ -133,6 +133,26 @@ bool ArmTranslatorVisitor::asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool
return true;
}
+bool ArmTranslatorVisitor::asimd_VQABS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
+ if (sz == 0b11) {
+ return UndefinedInstruction();
+ }
+
+ if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
+ return UndefinedInstruction();
+ }
+
+ const size_t esize = 8U << sz;
+ const auto d = ToVector(Q, Vd, D);
+ const auto m = ToVector(Q, Vm, M);
+
+ const auto reg_m = ir.GetVector(m);
+ const auto result = ir.VectorSignedSaturatedAbs(esize, reg_m);
+
+ ir.SetVector(d, result);
+ return true;
+}
+
bool ArmTranslatorVisitor::asimd_VABS(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
if (sz == 0b11 || (F && sz != 0b10)) {
return UndefinedInstruction();
diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h
index 094cda31..9460fff5 100644
--- a/src/frontend/A32/translate/impl/translate_arm.h
+++ b/src/frontend/A32/translate/impl/translate_arm.h
@@ -456,6 +456,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VCLZ(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
+ bool asimd_VQABS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VABS(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
bool asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
bool asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm);