diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index d145c153..04a67e2c 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -75,6 +75,7 @@ add_library(dynarmic frontend/A64/translate/impl/data_processing_shift.cpp frontend/A64/translate/impl/exception_generating.cpp frontend/A64/translate/impl/floating_point_compare.cpp + frontend/A64/translate/impl/floating_point_conversion_integer.cpp frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp frontend/A64/translate/impl/floating_point_data_processing_two_register.cpp frontend/A64/translate/impl/impl.cpp diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 870c8247..1eb5fc55 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -902,8 +902,8 @@ INST(EOR_asimd, "EOR (vector)", "0Q101 //INST(FCVTPU_float, "FCVTPU (scalar)", "z0011110yy101001000000nnnnnddddd") //INST(FCVTMS_float, "FCVTMS (scalar)", "z0011110yy110000000000nnnnnddddd") //INST(FCVTMU_float, "FCVTMU (scalar)", "z0011110yy110001000000nnnnnddddd") -//INST(FCVTZS_float_int, "FCVTZS (scalar, integer)", "z0011110yy111000000000nnnnnddddd") -//INST(FCVTZU_float_int, "FCVTZU (scalar, integer)", "z0011110yy111001000000nnnnnddddd") +INST(FCVTZS_float_int, "FCVTZS (scalar, integer)", "z0011110yy111000000000nnnnnddddd") +INST(FCVTZU_float_int, "FCVTZU (scalar, integer)", "z0011110yy111001000000nnnnnddddd") //INST(FJCVTZS, "FJCVTZS", "0001111001111110000000nnnnnddddd") // Data Processing - FP and SIMD - Floating point data processing diff --git a/src/frontend/A64/translate/impl/floating_point_conversion_integer.cpp b/src/frontend/A64/translate/impl/floating_point_conversion_integer.cpp new file mode 100644 index 00000000..2b90af38 --- /dev/null +++ b/src/frontend/A64/translate/impl/floating_point_conversion_integer.cpp @@ -0,0 +1,79 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2018 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#include + +#include "frontend/A64/translate/impl/impl.h" + +namespace Dynarmic::A64 { + +static boost::optional GetDataSize(Imm<2> type) { + switch (type.ZeroExtend()) { + case 0b00: + return 32; + case 0b01: + return 64; + case 0b11: + return 16; + } + return boost::none; +} + +bool TranslatorVisitor::FCVTZS_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) { + const size_t intsize = sf ? 64 : 32; + const auto fltsize = GetDataSize(type); + if (!fltsize || *fltsize == 16) { + return UnallocatedEncoding(); + } + + const IR::U32U64 fltval = V_scalar(*fltsize, Vn); + IR::U32U64 intval; + + if (intsize == 32 && *fltsize == 32) { + intval = ir.FPSingleToS32(fltval, true, true); + } else if (intsize == 32 && *fltsize == 64) { + intval = ir.FPDoubleToS32(fltval, true, true); + } else if (intsize == 64 && *fltsize == 32) { + return InterpretThisInstruction(); + } else if (intsize == 64 && *fltsize == 64) { + return InterpretThisInstruction(); + } else { + UNREACHABLE(); + } + + X(intsize, Rd, intval); + + return true; +} + +bool TranslatorVisitor::FCVTZU_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) { + const size_t intsize = sf ? 64 : 32; + const auto fltsize = GetDataSize(type); + if (!fltsize || *fltsize == 16) { + return UnallocatedEncoding(); + } + + const IR::U32U64 fltval = V_scalar(*fltsize, Vn); + IR::U32U64 intval; + + if (intsize == 32 && *fltsize == 32) { + intval = ir.FPSingleToU32(fltval, true, true); + } else if (intsize == 32 && *fltsize == 64) { + intval = ir.FPDoubleToU32(fltval, true, true); + } else if (intsize == 64 && *fltsize == 32) { + return InterpretThisInstruction(); + } else if (intsize == 64 && *fltsize == 64) { + return InterpretThisInstruction(); + } else { + UNREACHABLE(); + } + + X(intsize, Rd, intval); + + return true; +} + +} // namespace Dynarmic::A64 diff --git a/src/frontend/ir/ir_emitter.cpp b/src/frontend/ir/ir_emitter.cpp index 78e5472d..eb367382 100644 --- a/src/frontend/ir/ir_emitter.cpp +++ b/src/frontend/ir/ir_emitter.cpp @@ -979,12 +979,12 @@ U32 IREmitter::FPSingleToU32(const U32& a, bool round_towards_zero, bool fpscr_c return Inst(Opcode::FPSingleToU32, a, Imm1(round_towards_zero)); } -U32 IREmitter::FPDoubleToS32(const U32& a, bool round_towards_zero, bool fpscr_controlled) { +U32 IREmitter::FPDoubleToS32(const U64& a, bool round_towards_zero, bool fpscr_controlled) { ASSERT(fpscr_controlled); return Inst(Opcode::FPDoubleToS32, a, Imm1(round_towards_zero)); } -U32 IREmitter::FPDoubleToU32(const U32& a, bool round_towards_zero, bool fpscr_controlled) { +U32 IREmitter::FPDoubleToU32(const U64& a, bool round_towards_zero, bool fpscr_controlled) { ASSERT(fpscr_controlled); return Inst(Opcode::FPDoubleToU32, a, Imm1(round_towards_zero)); } diff --git a/src/frontend/ir/ir_emitter.h b/src/frontend/ir/ir_emitter.h index 3faefb21..932cc78d 100644 --- a/src/frontend/ir/ir_emitter.h +++ b/src/frontend/ir/ir_emitter.h @@ -245,8 +245,8 @@ public: U64 FPSingleToDouble(const U32& a, bool fpscr_controlled); U32 FPSingleToS32(const U32& a, bool round_towards_zero, bool fpscr_controlled); U32 FPSingleToU32(const U32& a, bool round_towards_zero, bool fpscr_controlled); - U32 FPDoubleToS32(const U32& a, bool round_towards_zero, bool fpscr_controlled); - U32 FPDoubleToU32(const U32& a, bool round_towards_zero, bool fpscr_controlled); + U32 FPDoubleToS32(const U64& a, bool round_towards_zero, bool fpscr_controlled); + U32 FPDoubleToU32(const U64& a, bool round_towards_zero, bool fpscr_controlled); U32 FPS32ToSingle(const U32& a, bool round_to_nearest, bool fpscr_controlled); U32 FPU32ToSingle(const U32& a, bool round_to_nearest, bool fpscr_controlled); U64 FPS32ToDouble(const U32& a, bool round_to_nearest, bool fpscr_controlled);