From f8f4f9abb49c6c631d44303561de536f119f4699 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Mon, 14 May 2018 09:12:56 -0400
Subject: [PATCH] A64: Implement LDR (literal, SIMD&FP)

---
 src/frontend/A64/decoder/a64.inc               |  2 +-
 .../translate/impl/load_store_load_literal.cpp | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index c11ceeb6..d2634c76 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -156,7 +156,7 @@ INST(LDAR,                   "LDARB, LDARH, LDAR",                        "zz001
 INST(LDR_lit_gen,            "LDR (literal)",                             "0z011000iiiiiiiiiiiiiiiiiiittttt")
 INST(LDRSW_lit,              "LDRSW (literal)",                           "10011000iiiiiiiiiiiiiiiiiiittttt")
 INST(PRFM_lit,               "PRFM (literal)",                            "11011000iiiiiiiiiiiiiiiiiiittttt")
-//INST(LDR_lit_fpsimd,         "LDR (literal, SIMD&FP)",                    "oo011100iiiiiiiiiiiiiiiiiiittttt")
+INST(LDR_lit_fpsimd,         "LDR (literal, SIMD&FP)",                    "oo011100iiiiiiiiiiiiiiiiiiittttt")
 
 // Loads and stores - Load/Store no-allocate pair
 //INST(STNP_gen,               "STNP",                                      "-010100000iiiiiiiuuuuunnnnnttttt")
diff --git a/src/frontend/A64/translate/impl/load_store_load_literal.cpp b/src/frontend/A64/translate/impl/load_store_load_literal.cpp
index 2d5c0e25..c1ee4bbc 100644
--- a/src/frontend/A64/translate/impl/load_store_load_literal.cpp
+++ b/src/frontend/A64/translate/impl/load_store_load_literal.cpp
@@ -20,6 +20,24 @@ bool TranslatorVisitor::LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt) {
     return true;
 }
 
+bool TranslatorVisitor::LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt) {
+    if (opc == 0b11) {
+        return UnallocatedEncoding();
+    }
+
+    const u64 size = 4 << opc.ZeroExtend();
+    const u64 offset = imm19.SignExtend<u64>() << 2;
+    const IR::U64 address = ir.Imm64(ir.PC() + offset);
+    const IR::UAnyU128 data = Mem(address, size, AccType::VEC);
+
+    if (size == 16) {
+        V(128, Vt, data);
+    } else {
+        V(128, Vt, ir.ZeroExtendToQuad(data));
+    }
+    return true;
+}
+
 bool TranslatorVisitor::LDRSW_lit(Imm<19> imm19, Reg Rt) {
     s64 offset = concatenate(imm19, Imm<2>{0}).SignExtend<s64>();