diff --git a/src/backend/A64/emit_a64_packed.cpp b/src/backend/A64/emit_a64_packed.cpp
index 0a39f5cd..83f77c38 100644
--- a/src/backend/A64/emit_a64_packed.cpp
+++ b/src/backend/A64/emit_a64_packed.cpp
@@ -341,4 +341,17 @@ void EmitA64::EmitPackedSaturatedSubS16(EmitContext& ctx, IR::Inst* inst) {
     code.fp_emitter.SQSUB(H, a, a, b);
     ctx.reg_alloc.DefineValue(inst, a);
 }
+
+void EmitA64::EmitPackedSelect(EmitContext& ctx, IR::Inst* inst) {
+    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
+
+    const ARM64Reg ge = EncodeRegToDouble(ctx.reg_alloc.UseScratchFpr(args[0]));
+    const ARM64Reg a = EncodeRegToDouble(ctx.reg_alloc.UseFpr(args[1]));
+    const ARM64Reg b = EncodeRegToDouble(ctx.reg_alloc.UseFpr(args[2]));
+
+    code.fp_emitter.BSL(ge, b, a);
+
+    ctx.reg_alloc.DefineValue(inst, ge);
+}
+
 } // namespace Dynarmic::BackendA64
diff --git a/src/backend/A64/opcodes.inc b/src/backend/A64/opcodes.inc
index 54368515..baac8dd3 100644
--- a/src/backend/A64/opcodes.inc
+++ b/src/backend/A64/opcodes.inc
@@ -213,7 +213,7 @@ OPCODE(PackedSaturatedAddS16,                               U32,            U32,
 OPCODE(PackedSaturatedSubU16,                               U32,            U32,            U32                                             )
 OPCODE(PackedSaturatedSubS16,                               U32,            U32,            U32                                             )
 //OPCODE(PackedAbsDiffSumS8,                                  U32,            U32,            U32                                             )
-//OPCODE(PackedSelect,                                        U32,            U32,            U32,            U32                             )
+OPCODE(PackedSelect,                                        U32,            U32,            U32,            U32                             )
 
 // CRC instructions
 //OPCODE(CRC32Castagnoli8,                                    U32,            U32,            U32                                             )
diff --git a/src/frontend/A32/decoder/arm_a64.inc b/src/frontend/A32/decoder/arm_a64.inc
index 69ae415a..90df5206 100644
--- a/src/frontend/A32/decoder/arm_a64.inc
+++ b/src/frontend/A32/decoder/arm_a64.inc
@@ -182,7 +182,7 @@ INST(arm_MOVT,          "MOVT",                "cccc00110100vvvvddddvvvvvvvvvvvv
 INST(arm_MOVW,          "MOVW",                "cccc00110000vvvvddddvvvvvvvvvvvv") // v6T2
 INST(arm_NOP,           "NOP",                 "----0011001000001111000000000000") // v6K
 INST(arm_SBFX,          "SBFX",                "cccc0111101wwwwwddddvvvvv101nnnn") // v6T2
-//INST(arm_SEL,           "SEL",                 "cccc01101000nnnndddd11111011mmmm") // v6
+INST(arm_SEL,           "SEL",                 "cccc01101000nnnndddd11111011mmmm") // v6
 INST(arm_UBFX,          "UBFX",                "cccc0111111wwwwwddddvvvvv101nnnn") // v6T2
 
 // Unsigned Sum of Absolute Differences instructions