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IR: Implement A64OrQC

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This commit is contained in:
MerryMage 2018-07-24 19:04:40 +01:00
parent 6fac68dd1d
commit ff025e88d0
5 changed files with 22 additions and 0 deletions
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15
src/backend_x64/a64_emit_x64.cpp
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@ -468,6 +468,21 @@ void A64EmitX64::EmitA64SetFPSR(A64EmitContext& ctx, IR::Inst* inst) {
code.ldmxcsr(code.dword[code.r15 + offsetof(A64JitState, guest_MXCSR)]); code.ldmxcsr(code.dword[code.r15 + offsetof(A64JitState, guest_MXCSR)]);
} }
void A64EmitX64::EmitA64OrQC(A64EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
if (args[0].IsImmediate()) {
if (!args[0].GetImmediateU1())
return;
code.mov(code.byte[code.r15 + offsetof(A64JitState, fpsr_qc)], u8(1));
return;
}
const Xbyak::Reg8 to_store = ctx.reg_alloc.UseGpr(args[1]).cvt8();
code.or_(code.byte[code.r15 + offsetof(A64JitState, fpsr_qc)], to_store);
}
void A64EmitX64::EmitA64SetPC(A64EmitContext& ctx, IR::Inst* inst) { void A64EmitX64::EmitA64SetPC(A64EmitContext& ctx, IR::Inst* inst) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst); auto args = ctx.reg_alloc.GetArgumentInfo(inst);
auto addr = qword[r15 + offsetof(A64JitState, pc)]; auto addr = qword[r15 + offsetof(A64JitState, pc)];

4
src/frontend/A64/ir_emitter.cpp
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@ -33,6 +33,10 @@ void IREmitter::SetNZCV(const IR::NZCV& nzcv) {
Inst(Opcode::A64SetNZCV, nzcv); Inst(Opcode::A64SetNZCV, nzcv);
} }
void IREmitter::OrQC(const IR::U1& value) {
Inst(Opcode::A64OrQC, value);
}
void IREmitter::CallSupervisor(u32 imm) { void IREmitter::CallSupervisor(u32 imm) {
Inst(Opcode::A64CallSupervisor, Imm32(imm)); Inst(Opcode::A64CallSupervisor, Imm32(imm));
} }

1
src/frontend/A64/ir_emitter.h
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@ -38,6 +38,7 @@ public:
void SetCheckBit(const IR::U1& value); void SetCheckBit(const IR::U1& value);
IR::U1 GetCFlag(); IR::U1 GetCFlag();
void SetNZCV(const IR::NZCV& nzcv); void SetNZCV(const IR::NZCV& nzcv);
void OrQC(const IR::U1& value);
void CallSupervisor(u32 imm); void CallSupervisor(u32 imm);
void ExceptionRaised(Exception exception); void ExceptionRaised(Exception exception);

1
src/frontend/ir/microinstruction.cpp
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@ -341,6 +341,7 @@ bool Inst::ReadsFromFPSRCumulativeSaturationBit() const {
bool Inst::WritesToFPSRCumulativeSaturationBit() const { bool Inst::WritesToFPSRCumulativeSaturationBit() const {
switch (op) { switch (op) {
case Opcode::A64OrQC:
case Opcode::VectorSignedSaturatedNarrowToSigned16: case Opcode::VectorSignedSaturatedNarrowToSigned16:
case Opcode::VectorSignedSaturatedNarrowToSigned32: case Opcode::VectorSignedSaturatedNarrowToSigned32:
case Opcode::VectorSignedSaturatedNarrowToSigned64: case Opcode::VectorSignedSaturatedNarrowToSigned64:

1
src/frontend/ir/opcodes.inc
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@ -59,6 +59,7 @@ A64OPC(SetQ, T::Void, T::A64Vec,
A64OPC(SetSP, T::Void, T::U64 ) A64OPC(SetSP, T::Void, T::U64 )
A64OPC(SetFPCR, T::Void, T::U32 ) A64OPC(SetFPCR, T::Void, T::U32 )
A64OPC(SetFPSR, T::Void, T::U32 ) A64OPC(SetFPSR, T::Void, T::U32 )
A64OPC(OrQC, T::Void, T::U1 )
A64OPC(SetPC, T::Void, T::U64 ) A64OPC(SetPC, T::Void, T::U64 )
A64OPC(CallSupervisor, T::Void, T::U32 ) A64OPC(CallSupervisor, T::Void, T::U32 )
A64OPC(ExceptionRaised, T::Void, T::U64, T::U64 ) A64OPC(ExceptionRaised, T::Void, T::U64, T::U64 )