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1581 Commits

Author SHA1 Message Date
Lioncash
13b41525cb
frontend/ir_emitter: Add half-precision opcode for FPMulAdd 2019-04-13 00:18:09 -04:00
Lioncash
2ae0c4807a
fp/op/FPMulAdd: Add half-precision floating-point specialization 2019-04-13 00:07:34 -04:00
Merry
ed8c218076
Merge pull request #471 from lioncash/sqrdmulh 
A64: Implement SQRDMULH's scalar vector variant
 2019-04-12 20:29:22 +01:00
Merry
c963996e0b
Merge pull request #470 from lioncash/assert 
general: Replace unreachable-imitating assertions with UNREACHABLE()
 2019-04-12 20:14:18 +01:00
Lioncash
f58406333a
A64: Implement SQRDMULH's scalar vector variant 
Implements the scalar variant in terms of the vector variant for the
time being.
 2019-04-12 15:05:53 -04:00
Lioncash
a5ca872208
general: Replace unreachable-imitating assertions with UNREACHABLE() 
We can just use the self-documenting assertion for indicating
unreachable paths, instead of manually passing false and providing a
message.
 2019-04-12 14:51:43 -04:00
Lioncash
d75af9d0e1
A64/impl: Reorganize peculiar void use in V_scalar 
To a reader this might look particularly strange, given the function
itself has a void return value, but this is actually valid, given the
function in the return statement also has a void return value.

This instead alters it to be a little easier to parse and potentially be
a little less confusing at a glance.
 2019-04-12 14:44:16 -04:00
Merry
4ed7009f24
Merge pull request #468 from lioncash/const 
ir_opt: Mark locals as const where applicable
 2019-04-12 19:15:32 +01:00
Merry
25039d02ff
Merge pull request #467 from lioncash/reserved 
A64: Handle reserved instruction cases more specifically where applicable
 2019-04-12 19:13:08 +01:00
Merry
5fdbb46008
Merge pull request #466 from lioncash/fcmla 
A64: Implement FCMLA's indexed element variant
 2019-04-12 08:15:05 +01:00
Lioncash
e244bf4f68
ir_opt/verification_pass: Mark locals as const where applicable 
Makes our immutable state a little more explicit.
 2019-04-11 18:30:30 -04:00
Lioncash
d02eef2fac
ir_opt/a64_callback_config_pass: Mark locals as const where applicable 
Makes our immutable state a little more explicit.
 2019-04-11 18:28:11 -04:00
Lioncash
38977fac33
ir_opt/a32_get_set_elimination_pass: Mark local variables as const where applicable 
Makes our intended immutable state slightly more explicit.
 2019-04-11 18:26:13 -04:00
Lioncash
e299e92698
ir_opt/a32_constant_memory_reads_pass: Apply const where applicable to locals 
Makes immutable state just slightly more explicit.
 2019-04-11 18:18:32 -04:00
Lioncash
0dca81d20f
A64: Handle reserved instruction cases more specifically where applicable 
These are cases that are defined as reserved within the ARMv8 reference
manual, so we can handle them as such instead of as unallocated
encodings.

While this doesn't actually change emulated behavior, it does at least
allow the JIT to generate the more appropriate exception.
 2019-04-11 17:47:28 -04:00
Lioncash
06e7e9fbef
A64: Implement FCMLA's indexed element variant 
With this, all of the instructions introduced with ARMv8.3-CompNum have
an implementation.
 2019-04-11 17:20:06 -04:00
Merry
c635591355
Merge pull request #465 from neobrain/master 
CMakeLists: Allow importing dynarmic build trees into other CMake projects
 2019-04-11 22:00:46 +01:00
Tony Wasserka
fd4fa20834 CMakeLists: Allow importing dynarmic build trees into other CMake projects 2019-04-11 18:04:57 +02:00
Lioncash
b7a76d6967
simd_scalar_shift_by_immediate: Change UnallocatedEncoding() path in SaturatingShiftLeft to ReservedValue() 
Strictly speaking, immh being zero is defined as reserved in the ARMv8
reference manual. This was just an error on my part when introducing the
SQSHL immediate scalar variant.
 2019-04-10 15:20:11 -04:00
Lioncash
2769572231
A64: Implement UQSHL (immediate)'s scalar variant 
Like SQSHL's immediate scalar variant, we can also implement UQSHL's
immediate scalar variant in terms of the vector variant for the time
being.
 2019-04-10 15:12:57 -04:00
Lioncash
24479ecbe5
simd_scalar_shift_by_immediate: Migrate SQSHL implementation to file-scope function 
This will allow it to be reused for the implementation of UQSHL.
 2019-04-10 15:10:32 -04:00
Lioncash
fc729bee8c
A64: Implement scalar variant of SQSHL (immediate) 
This can be handled in terms of the vector variant for the time being.
 2019-04-09 10:13:14 -04:00
Lioncash
06ac561e1c
backend/x64/emit_x64_vector: Prevent undefined behavior within VectorSignedSaturatedShiftLeft 
Avoids undefined behavior by potentially left-shifting a signed negative
value.
 2019-04-01 19:53:48 -04:00
Lioncash
f4d63ff07d
common/fp/op/FPRecipExponent: Prevent undefined behavior from shifting a negative value 
Due to promotion rules (types < int, even if unsigned, get promoted to
int when arithmetic is performed on them), this is a potential spot for
undefined behavior.
 2019-04-01 19:51:52 -04:00
MerryMage
a1f642f838 emit_x64_floating_point: F16C implementation of FPSingleToHalf 2019-03-24 15:42:14 +00:00
MerryMage
2a5b4f4933 emit_x64_floating_point: F16C implementation of FPHalfToSingle and FPHalfToDouble 2019-03-24 11:42:22 +00:00
MerryMage
59887e8b62 emit_x64_floating_point: Factor out ConvertRoundingModeToX64Immediate 2019-03-24 11:28:04 +00:00
MerryMage
16a40b3b9d backend/x64: Expose FPCR in EmitContext instead of its subcomponents 2019-03-24 11:28:04 +00:00
Merry
d5263c17cb
Merge pull request #458 from lioncash/float-op 
A64: Handle half-precision floating point in FABS, FNEG, and scalar FMOV
 2019-03-24 11:23:21 +00:00
Lioncash
f12b0f926c
A64: Handle half-precision floating point in FCVTL 
Like FCVTN, now that we have half-precision floating point conversion
functions available, we can go ahead and use those to eliminate the
interpreter fallback.
 2019-03-23 14:16:44 -04:00
Lioncash
d4d642198c
A64: Handle half-precision floating point in FCVTN 
Now that we have IR instructions for performing conversions with
half-precision floating point, we can also handle half-precision values
within FCVTN.
 2019-03-23 14:16:44 -04:00
Lioncash
ede3d7284a
A64: Enable FCVT floating-point conversions for half-precision 
With this, we no longer have to fall back to the interpreter in any of
the FCVT floating-point conversion instructions.
 2019-03-23 14:16:44 -04:00
Lioncash
eb09ae27db
frontend/ir_emitter: Add half->{single, double} and {double, single}->half conversion opcodes 2019-03-23 14:16:44 -04:00
Lioncash
f74c9dad6f
common/fp/unpacked: Amend behavior of FPUnpackCV 
This is supposed to call FPUnpackBase instead of FPUnpack. This would
result in alternate half-precision representations being misinterpreted
when it comes to dealing with NaNs.
 2019-03-23 14:16:44 -04:00
Lioncash
36e739ba9b
common/fp/op/FPConvert: Amend off-by one in double NaN case in FPConvertNaN 
Avoids potentially clobbering the intended sign bit value during
conversions to double-precision values. The other conversion types are
already properly handled, so those don't need to be addressed.
 2019-03-23 14:16:44 -04:00
Lioncash
29e1a024c7
common/fp/op/FPConvert: Add half-precision instantiations to FPConvert 2019-03-23 14:16:37 -04:00
Lioncash
d59cff531c
A64: Handle half-precision floating point in scalar FMOV 
This is simply performing a scalar value transfer between registers
without conversions, so this is trivial to handle as-is.
 2019-03-23 13:46:47 -04:00
Lioncash
5196e94792
A64: Handle half-precision floating point in scalar FABS 
Now that we have the half-precision variant of the opcode added, we can
simply handle the instruction instead of treating it as undefined.
 2019-03-23 13:39:23 -04:00
Lioncash
c75f73785d
frontend/ir_emitter: Add half-precision variant of FPAbs 2019-03-23 13:38:09 -04:00
Lioncash
b772cb7c5a
A64: Handle half-precision floating point in scalar FNEG 
With the half-precision variant of the FPNeg opcode added, we can
utilize it here to emulate the half-precision variant of FNEG.
 2019-03-23 13:23:34 -04:00
Lioncash
fd71df5efd
frontend/ir_emitter: Add half-precision variant of FPNeg 2019-03-23 13:21:59 -04:00
Merry
0f2f6ef789
Merge pull request #456 from lioncash/mov 
A64: Enable FMOV (general) for half-precision floating point
 2019-03-22 22:27:48 +00:00
Lioncash
7627fa389b
A64: Enable FMOV (general) for half-precision floating point 
This just transfers values between vector registers and general-purpose
registers with no conversions performed, so this is trivial to add
support for half-precision to.
 2019-03-22 15:18:12 -04:00
Merry
004adfe844
Merge pull request #455 from lioncash/sqrdmulh-scalar 
A64: Implement SQRDMULH and SQDMULL's scalar indexed variants
 2019-03-22 12:43:53 +00:00
Lioncash
5c6becc402
A64: Implement SQRDMULH's scalar indexed element variant 2019-03-20 23:26:55 -04:00
Lioncash
2d78390d43
A64: Implement SQDMULL{2}'s scalar indexed element variant 2019-03-20 23:05:07 -04:00
Lioncash
3238864878
simd_scalar_x_indexed_element: Factor out index and Vm argument construction 
This will be useful in the implementations of SQRDMULH and SQDMULL{2} as
well.
 2019-03-20 22:28:46 -04:00
Lioncash
996a618643
simd_vector_x_indexed_element: Deduplicate index and Vm operand construction 2019-03-20 16:21:48 -04:00
Lioncash
328211b0c5
A64: Implement SQDMULL{2}'s by-element variant 2019-03-20 15:36:27 -04:00
Lioncash
b4ca6b67d1
A64: Implement SQRDMULH's by-index vector variant 2019-03-20 14:05:41 -04:00