MerryMage
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727b1b0b51
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A64: Implement MUL (vector)
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2018-02-11 10:18:47 +00:00 |
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MerryMage
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80fce9c4b9
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IR: Implement VectorMultiply
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2018-02-11 10:18:29 +00:00 |
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MerryMage
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cb65a26da2
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emit_x64_vector: Order alphabetically
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2018-02-11 09:41:37 +00:00 |
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MerryMage
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2b968981a1
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A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
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2018-02-11 01:06:26 +00:00 |
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MerryMage
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7681159811
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decoder/a64: Don't rearrange unrelated decoders
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2018-02-11 00:43:33 +00:00 |
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MerryMage
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56fe848e4e
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A64: Implement SUB (vector)
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2018-02-10 23:58:33 +00:00 |
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MerryMage
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b429efa081
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A64: Implement SIMD instruction SSRA, vector variant
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2018-02-10 23:30:00 +00:00 |
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MerryMage
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0a96a437cb
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A64: Implement SIMD instruction SSHR, vector variant
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2018-02-10 23:28:05 +00:00 |
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MerryMage
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a5299d0be5
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IR: Implement VectorArithmeticShiftRight
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2018-02-10 23:27:46 +00:00 |
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MerryMage
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8e8068cfaf
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impl: Improve Vpart setter
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2018-02-10 17:05:52 +00:00 |
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MerryMage
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5ffa84f41d
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A64: Implement SIMD instructions XTN, XTN2
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2018-02-10 17:01:33 +00:00 |
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MerryMage
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dc9785bdcd
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IR: Implement VectorNarrow
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2018-02-10 17:01:33 +00:00 |
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MerryMage
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ebc594385c
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constant_pool: Allow for 128-bit constants
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2018-02-10 16:36:00 +00:00 |
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MerryMage
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8e23683b63
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emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
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2018-02-10 16:24:43 +00:00 |
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MerryMage
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d9f803924e
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IR: Implement VectorSub
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2018-02-10 11:25:50 +00:00 |
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MerryMage
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c01bbbd09d
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A64: Implement SIMD instruction USRA, vector variant
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2018-02-10 11:12:54 +00:00 |
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MerryMage
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9e80f94b5f
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A64: Implement SIMD instruction USHR, vector variant
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2018-02-10 11:05:58 +00:00 |
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MerryMage
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e6a0a4d8ce
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IR: Implement VectorLogicalShiftRight
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2018-02-10 11:05:22 +00:00 |
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MerryMage
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60ddaa8f38
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A64: Implement SIMD instructions USHLL, USHLL2
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2018-02-10 10:35:14 +00:00 |
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MerryMage
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670b47149e
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IR: Implement VectorZeroExtend
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2018-02-10 10:35:14 +00:00 |
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MerryMage
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7ec12cbade
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IR: Vector instructions now take esize argument in emitter
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2018-02-10 10:18:10 +00:00 |
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MerryMage
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b219105b75
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A64: Implement SIMD instruction SHL
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2018-02-10 09:49:55 +00:00 |
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MerryMage
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570911e693
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IR: Implement VectorLogicalShiftLeft{8,16,32,64}
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2018-02-10 09:31:54 +00:00 |
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MerryMage
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e03a9fed98
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opcodes: Sort vector IR opcodes alphabetically
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2018-02-10 09:15:01 +00:00 |
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MerryMage
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406c071008
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block_of_code: Increase constant pool size
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2018-02-09 16:04:56 +00:00 |
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MerryMage
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9be412bbc2
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devirtualize: MinGW uses Intanium MFP ABI
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2018-02-09 16:04:48 +00:00 |
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MerryMage
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7a0fdf01bb
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callback: Properly handle calls with return pointers and simplify interface
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2018-02-09 16:02:57 +00:00 |
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FernandoS27
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dee211c4df
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Implemented BSL, BIC, BIT and BIF vector instructions
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2018-02-09 13:28:16 +00:00 |
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MerryMage
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15da38d3aa
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devirtualize: Handle Windows ABI
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2018-02-09 11:19:40 +00:00 |
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MerryMage
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41ae12263d
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travis: Switch to yuzu-emu's unicorn repository
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2018-02-08 19:48:04 +00:00 |
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MerryMage
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83a762eee7
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fuzz_arm: Use SCOPE_FAIL
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2018-02-08 02:14:42 +00:00 |
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MerryMage
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b0991ee46f
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A32/decoder/arm: bug: Correct bitstring for SRS
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2018-02-08 02:05:49 +00:00 |
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MerryMage
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43035fd064
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devirtualize: Devirtualize Itanium ABI MFPs at runtime
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2018-02-07 12:25:45 +00:00 |
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MerryMage
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36ec1d09cf
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cast_util: Add BitCast and BitCastPointee
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2018-02-07 12:25:45 +00:00 |
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Lioncash
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1ee5b2e352
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A64: Move SDIV and UDIV out of data_processing_multiply.cpp
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2018-02-07 12:07:09 +00:00 |
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Lioncash
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25e7c94995
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A64: Implement ZIP1
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2018-02-07 12:06:49 +00:00 |
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FernandoS27
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c882e6819d
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Implemented UMULH and SMULH instructions
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2018-02-06 23:59:24 +00:00 |
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MerryMage
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32be42c68e
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A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
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2018-02-06 23:29:18 +00:00 |
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MerryMage
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b6775f1282
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impl: Add AdvSIMDExpandImm
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2018-02-06 23:04:23 +00:00 |
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MerryMage
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023c2c9818
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A64: Implement SUB (vector), scalar variant
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2018-02-06 22:12:39 +00:00 |
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MerryMage
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b544b8f4b1
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A64: Implement ADD (vector), scalar variant
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2018-02-06 22:09:39 +00:00 |
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MerryMage
|
63d3a1cc1c
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A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
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2018-02-06 18:30:36 +00:00 |
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MerryMage
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59a84ed966
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A64: Implement BIC (vector, register)
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2018-02-06 17:57:50 +00:00 |
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MerryMage
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41bbb56cff
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docs: Update documentation (2018-02-05)
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2018-02-05 22:36:03 +00:00 |
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MerryMage
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8530f52729
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A64: Implement FMOV (general)
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2018-02-05 21:44:20 +00:00 |
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MerryMage
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ef9057555b
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translate/impl: Add Vpart
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2018-02-05 21:43:58 +00:00 |
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MerryMage
|
37b4840c6f
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A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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2018-02-05 15:41:41 +00:00 |
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MerryMage
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a785d4fa66
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A64: Implement FCCMPE
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2018-02-05 12:26:19 +00:00 |
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MerryMage
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d2a2562a25
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A64: Implement FCCMP
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2018-02-05 12:26:19 +00:00 |
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MerryMage
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24178131a6
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a64_jitstate: Remove unnecessary FPSCR_nzcv member
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2018-02-05 12:26:19 +00:00 |
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