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Author SHA1 Message Date
MerryMage
853bdd6b98 fp: A64::FPCR -> FP::FPCR 2018-07-20 11:39:39 +01:00
MerryMage
faa3ea2f2a bit_util: Implement ClearBits and ModifyBits 2018-07-20 11:39:30 +01:00
MerryMage
f659f0fb5c system: Simplify static_cast 2018-07-19 12:03:23 +01:00
Lioncash
9db6794f59 externals: Update Xbyak to 5.65 2018-07-19 10:43:26 +01:00
MerryMage
5a91c94dca system: Ensure value of CNTPCT_EL0 is accurate 
Since we currently only update the host's tick count at the end of a
block, we force an end-of-block before executing a MRS %, CNTPCT_ELO
instruction.
 2018-07-19 02:37:28 +01:00
Lioncash
1e303aa1f3 safe_ops: Avoid cases where shift bases are invalid with signed values 
For example, say the converted signed type is s64, shifting left  by 63
bits would be undefined behavior.

However, given an ASL is essentially the same behavior as an LSL
we can just use an unsigned type instead of converting to a signed type.
 2018-07-17 21:24:34 +01:00
Lioncash
e3d533d954 safe_ops: Avoid signed overflow in Negate() 
Negation of values such as -9223372036854775808 can't be represented in
signed equivalents (such as long long), leading to signed overflow.
Therefore, we can just invert bits and add 1 to perform this behavior
with unsigned arithmetic.
 2018-07-17 21:24:34 +01:00
Lioncash
6bf7280179 simd_scalar_shift_by_immediate: Implement FCVT{ZS, ZU} (vector, fixed-point)'s scalar double/single-precision variant 2018-07-17 19:45:58 +01:00
Lioncash
be860cf7e1 simd_scalar_two_register_misc: Implement FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU} (vector)'s scalar double/single-precision variants 
We can simply implement this in terms of the fixed-point IR opcodes.
 2018-07-17 19:45:58 +01:00
Lioncash
cae96d1da5 tests: Silence warnings in skyeye code 
Gets rid of warning noise when compiling the tests.
 2018-07-17 19:44:10 +01:00
Lioncash
adbb8964c6 emit_x64: Remove FPSCR_RoundTowardsZero() virtual function from EmitContext struct 
This code was bugged in that we were comparing if the rounding mode was
not equal to rounding towards zero. Fortunately, however, nothing uses
this function anymore, and there's already the more general
FPSCR_RMode() available, so this can be removed entirely.
 2018-07-17 19:27:33 +01:00
Lioncash
6bcc766729 emit_x64: Add missing <array> include 
Commit 755adef62e504a8d616de9dda8937d2428a9471b introduced a helper
alias for std::array, eliminating the need to manually type out sizes
for them, however I forgot to add the include for <array>
 2018-07-17 19:00:00 +01:00
Lioncash
755adef62e emit_x64_vector{_floating_point}: Add helper alias for sizing arrays relative to vector width 
Avoids needing to remember to specify the proper size of the arrays, all
that's needed is to specify the type of the array and the size will
automatically be deduced from it. This helps prevent potential oversized
or undersized arrays from being specified.
 2018-07-17 17:54:22 +01:00
MerryMage
0c3b6bd11f A64/PopRSBHint: Prevent RETing to a guest PC of ~0ull from crashing the jit 2018-07-16 18:29:25 +01:00
MerryMage
5ae55914e2 tests: Add FABD test 2018-07-16 16:55:26 +01:00
MerryMage
39958434b6 A64: Implement FABD in terms of existing IR instructions 
Fixes NaN issue. Closes #306.
 2018-07-16 16:51:16 +01:00
MerryMage
4a3453179b FPRoundInt: Final FPRound based on new sign 
While this shouldn't change any of the results in theory, it's just logically more consistent
 2018-07-16 15:07:26 +01:00
MerryMage
5879b5f73f emit_x64_floating_point: SSE4.1 implementation of EmitFPRound 2018-07-16 14:22:29 +01:00
MerryMage
a981d3ffb1 A64: Implement FRINTX, FRINTI (scalar) 2018-07-16 14:10:53 +01:00
MerryMage
aa315c97b9 A64: Implement FRINTP, FRINTM, FRINTZ (scalar) 2018-07-16 14:10:53 +01:00
MerryMage
80aa4f49e6 A64: Implement FRINTN (scalar) 2018-07-16 14:10:53 +01:00
MerryMage
eaf4106620 A64: Implement FRINTA (scalar) 2018-07-16 14:10:53 +01:00
MerryMage
48166d80cd IR: Implement FPRoundInt 2018-07-16 14:10:53 +01:00
MerryMage
f600f48bdd fp: Implement FPRoundInt 2018-07-16 13:50:37 +01:00
MerryMage
a8952a521b fp: Implement FPProcessNaN 2018-07-16 13:50:37 +01:00
MerryMage
4ba4ed2dca fp/info: Add DefaultNaN 2018-07-16 13:50:37 +01:00
MerryMage
b08e49d337 fp: Move FPToFixed to its own file 2018-07-16 13:50:37 +01:00
MerryMage
814092c5be a64_jit_state: Add FPSR.QC flag 2018-07-16 13:50:37 +01:00
Lioncash
54c6d119ba emit_x64_vector: Use non-scratch Use* variants of registers within EmitVectorUnsignedAbsoluteDifference() 
In some cases, a register isn't modified, depending on the branch taken,
so we can signify this by using the non-scratch variants in certain
cases.
 2018-07-16 10:35:51 +01:00
Lioncash
ca579d2603 simd_scalar_two_register_misc: Implement scalar double/single-precision variants of FCM{EQ, GE, GT, LE, LT} (zero) 2018-07-16 10:35:26 +01:00
Lioncash
3b3e1c0991 translate_arm: Remove unnecessary rotr() function 
We already have RotateRight() in our common code, so we can remove this
function and replace it with it. We can also implement ArmExpandImm_C()
in terms of ArmExpandImm().
 2018-07-16 10:32:46 +01:00
Merry
dda07710e1
Merge pull request #309 from lioncash/typename 
cast_util: Remove unnecessary typename
 2018-07-16 10:18:03 +01:00
Lioncash
13df147ffb
cast_util: Remove unnecessary typename 
Given we use std::aligned_storage_t, we don't need to specify
typename here. If we used std::aligned_storage, then we would need to.
 2018-07-15 19:38:02 -04:00
MerryMage
41074a2547 A64: Implement FADDP (scalar) 2018-07-15 22:49:58 +01:00
MerryMage
59e78dc57e A64: Implement FADDP (vector) 2018-07-15 22:49:58 +01:00
MerryMage
dfdec797e3 A64: Implement SADDLP 2018-07-15 18:50:09 +01:00
MerryMage
3bb6a432d8 A64: Implement UADDLP 2018-07-15 18:26:54 +01:00
MerryMage
c103a28386 A64: Implement EXT 2018-07-15 17:47:32 +01:00
Merry
f23475764f
Merge pull request #289 from MerryMage/fptofixed 
Implement most of the scalar fp -> integer instructions
 2018-07-15 17:12:52 +01:00
MerryMage
d870a75417 emit_x64_floating_point: SSE4.1 implementation for FP{Double,Single}ToFixed{S,U}{32,64} 2018-07-15 17:03:40 +01:00
MerryMage
f0910c357a A64: Implement FCVTMU (scalar) 2018-07-15 15:37:29 +01:00
MerryMage
dd6772786e A64: Implement FCVTMS (scalar) 2018-07-15 15:37:29 +01:00
MerryMage
5b82fa8018 A64: Implement FCVTPU (scalar) 2018-07-15 15:37:29 +01:00
MerryMage
79c4e922db A64: Implement FCVTPS (scalar) 2018-07-15 15:37:29 +01:00
MerryMage
128db2f62a A64: Implement FCVTAU (scalar) 2018-07-15 15:37:29 +01:00
MerryMage
bb92f95b9d A64: Implement FCVTAS (scalar) 2018-07-15 15:37:29 +01:00
MerryMage
8cad14eee6 A64: Implement FCVTNU (scalar) 2018-07-15 15:37:29 +01:00
MerryMage
d3e8cf3e15 A64: Implement FCVTNS (scalar) 2018-07-15 15:37:29 +01:00
MerryMage
ec0c7e1acd floating_point_conversion_integer: Refactor implementation of FCVTZS_float_int and FCVTZU_float_int 2018-07-15 15:37:29 +01:00
MerryMage
2f567fe003 IR: Initial implementation of FP{Double,Single}ToFixed{S,U}{32,64} 
This implementation just falls-back to the software floating point implementation.
 2018-07-15 15:37:29 +01:00