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816 Commits

Author SHA1 Message Date
Lioncash
cdb588dab5 General: Default constructors and destructors where applicable 2018-01-24 09:07:22 +00:00
Lioncash
e300f1de46 ir_emitter: Remove unused includes 2018-01-24 01:50:10 +00:00
Lioncash
0e5988258d A64: Implement RBIT 2018-01-24 01:49:58 +00:00
MerryMage
ae603909d6 ir_emitted: Remove unimplemented IR instruction Unimplemented 2018-01-23 22:16:15 +00:00
MerryMage
f014a5bec7 emit_x64: Extract BlockRangeInformation, remove template parameter 2018-01-23 19:44:35 +00:00
MerryMage
5f5e664a66 emit_x64: Use JitStateInfo 2018-01-23 19:44:35 +00:00
MerryMage
d52cb2d0de A64: Implement CLS 
This is not the cleanest implementation.
 2018-01-23 19:44:35 +00:00
MerryMage
24383e543b A64: Implement ADDP (vector) 2018-01-23 17:46:28 +00:00
MerryMage
dfcbe5bd2f IR: Implement Vector{Lower,}PairedAdd{8,16,32,64} 2018-01-23 17:46:28 +00:00
MerryMage
961e64dfaf backend_x64: Split emit_x64 2018-01-23 17:46:28 +00:00
MerryMage
2b59e2ba0b microinstruction: bug: Add missing opcodes 2018-01-23 17:46:28 +00:00
Lioncash
bd00d9bc80 A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL 2018-01-23 16:08:05 +00:00
Lioncash
768e5bcf9c A64: Implement MADD and MSUB 2018-01-23 16:08:05 +00:00
Lioncash
ffaf837e58 A64: Implement CLZ 2018-01-23 11:55:09 +00:00
Lioncash
585e77d20e opcodes: Add 64-bit CountLeadingZeroes opcode 2018-01-23 11:55:09 +00:00
MerryMage
f2dc9c7727 data_processing_register: Clean-up 2018-01-22 22:47:01 +00:00
Lioncash
efa67caf5f A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL 
Truly the most difficult A64 instructions to implement.
 2018-01-22 11:54:12 +00:00
Lioncash
692cd6f27b A64: Implement ASRV, LSLV, LSRV, and RORV 2018-01-22 11:51:46 +00:00
Lioncash
a5978a01ca data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG 2018-01-21 23:33:18 +00:00
Lioncash
48e4e021f7 a32/a64_emit_x64: Remove unused includes 2018-01-21 20:09:23 +00:00
MerryMage
a6d17e6bb0 A64: Implement AND (vector) 2018-01-21 18:27:06 +00:00
MerryMage
d333b5dcee A64: Implement ADD (vector, vector) 2018-01-21 17:56:27 +00:00
Thomas Guillemard
1cf87a24b2 A64: Implement REV, REV32, and REV16 (#126) 2018-01-21 12:17:47 +00:00
MerryMage
9fc1570788 IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
 2018-01-19 01:09:46 +00:00
MerryMage
50c18181aa reg_alloc: GetBitWidth: Add UNREACHABLE 2018-01-18 23:46:01 +00:00
MerryMage
adccbf3c6b reg_alloc: Consider bitwidth of data and registers when emitting instructions 2018-01-18 13:00:16 +00:00
MerryMage
7b7f239831 A64: Implement CSEL 2018-01-18 11:41:27 +00:00
MerryMage
2f84137f5b IR: Implement Conditional Select 2018-01-18 11:36:52 +00:00
MerryMage
0892b487b7 A64/translate/branch: bug: Read-after-write error in BLR 2018-01-17 00:34:33 +00:00
MerryMage
e77bc26945 A64: Implement SBFM, BFM, UBFM 2018-01-17 00:15:44 +00:00
MerryMage
0c37ca71c6 A64: Implement MOVN, MOVZ, MOVK 2018-01-15 21:47:28 +00:00
MerryMage
a04ca20a89 ir/location_descriptor: Add missing <functional> header for std::hash 2018-01-14 20:23:24 +00:00
MerryMage
bc73004dd5 a64_merge_interpret_blocks: Remove debug output 2018-01-13 22:05:05 +00:00
MerryMage
fd9530be25 A64: Optimization: Merge interpret blocks 2018-01-13 21:57:18 +00:00
MerryMage
5218ad97e2 A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate 2018-01-13 18:06:06 +00:00
MerryMage
b1a8c39c19 A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31 2018-01-13 18:06:06 +00:00
MerryMage
64827fbe8e a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers 2018-01-13 18:06:06 +00:00
MerryMage
1bfa04d7ac emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64 2018-01-13 18:06:06 +00:00
MerryMage
9ab130490b A64: Add ExceptionRaised IR instruction 
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
 2018-01-13 18:06:06 +00:00
MerryMage
7438d07f2b A64/translate: Add TranslateSingleInstruction function 2018-01-12 19:34:25 +00:00
MerryMage
83afe4353c Misc. fixups of MSVC build 2018-01-12 18:13:53 +00:00
MerryMage
ad95a75047 imm: Suppress MSVC warning C4244: value will never be truncated 2018-01-12 17:18:07 +00:00
MerryMage
ebaeceec37 fixup! imm: compiler bug: MSVC 19.12 2018-01-12 17:11:42 +00:00
MerryMage
3a0b7d59f0 imm: compiler bug: MSVC 19.12 with /permissive- flag doesn't support fold expressions 2018-01-12 17:01:21 +00:00
MerryMage
dd285abec5 A64/decoder: Split decoder data from header 2018-01-11 13:03:56 +00:00
MerryMage
30af089e49 ir_opt: Split off A32 specific passes 2018-01-11 13:03:56 +00:00
MerryMage
648212995c A64: Implement LDP, STP 2018-01-11 13:03:54 +00:00
MerryMage
192e7a73ea A64/location_descriptor: Fix -fpermissive warning on GCC 2018-01-10 18:56:12 +00:00
MerryMage
89bdade0a0 A64: Implement LDP, STP 2018-01-10 02:05:08 +00:00
MerryMage
16e50ca0db A32: Implement load stores (immediate) 2018-01-10 01:30:30 +00:00