Lioncash
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33bc59c55a
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A64: Implement AESE
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2018-02-03 23:11:46 +00:00 |
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MerryMage
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db6999fc38
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backend_x64: Use a reference to BlockOfCode instead of a pointer
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2018-02-03 14:28:57 +00:00 |
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MerryMage
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a7209dc2f7
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IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
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2018-02-03 13:41:36 +00:00 |
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MerryMage
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2262b08a04
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A64: Implement INS (general)
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2018-02-03 13:07:00 +00:00 |
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MerryMage
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3c140141db
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A64: Implement INS (element)
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2018-02-03 13:03:50 +00:00 |
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MerryMage
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af5fb0a1a0
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A64: Implement SMOV
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2018-02-03 12:58:19 +00:00 |
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MerryMage
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818b9a4673
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A64: Implement UMOV
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2018-02-03 12:55:53 +00:00 |
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MerryMage
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9ea219e010
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basic_block: Fix bogus GCC maybe-uninitialized warning
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2018-02-03 03:04:44 +00:00 |
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MerryMage
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64e37de179
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A64: Implement FCVT
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2018-02-03 01:23:11 +00:00 |
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MerryMage
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f1d2cdde34
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fuzz_with_unicorn: Skip instructions that need to be interpreted
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2018-02-03 01:22:40 +00:00 |
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MerryMage
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2fd70e56ce
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A64: Implement FMOV (scalar, immediate)
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2018-02-03 00:52:48 +00:00 |
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MerryMage
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567c1b57fc
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A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
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2018-02-02 22:39:24 +00:00 |
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MerryMage
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c42ca435ba
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A64: Implement FCMP, FCMPE
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2018-02-02 22:25:51 +00:00 |
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MerryMage
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0131a87c43
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a64_jitstate: A64 does not have a seperate FPSCR.NZCV
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2018-02-02 22:25:18 +00:00 |
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MerryMage
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4728257d4e
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A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
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2018-02-02 22:04:09 +00:00 |
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MerryMage
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fcabd95ad0
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IR: Merge U32 and U64 variants of FP instructions
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2018-02-02 21:55:23 +00:00 |
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MerryMage
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6d9adb668e
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A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2018-02-02 21:10:30 +00:00 |
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MerryMage
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bfeb9ff617
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emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1
This bug wasn't discovered earlier because we previously only used index == 0.
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2018-02-02 21:07:00 +00:00 |
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MerryMage
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cc40b83ed0
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IR: Implement VectorSetElement{8,16,32,64}
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2018-02-02 21:00:12 +00:00 |
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Lioncash
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b608979be9
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A64: Implement AESIMC and AESMC
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2018-02-02 17:35:16 +00:00 |
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Lioncash
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58598e2e15
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iterator_util: Make Reverse constexpr
C++17 makes non-member rbegin(), rend(), crbegin(), and crend() constexpr, allowing this to also be constexpr.
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2018-01-31 18:09:15 +00:00 |
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Lioncash
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c9da41884c
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Common: Relocate common bits of CRC32
Allows the algorithm to be used in any other potential backend.
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2018-01-30 07:57:29 +00:00 |
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Lioncash
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7fb386aa1c
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A64: Implement CRC32
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2018-01-29 17:06:17 +00:00 |
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MerryMage
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4cc2cecaff
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scope_exit: Add SCOPE_SUCCESS and SCOPE_EXIT
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2018-01-28 18:03:58 +00:00 |
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MerryMage
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607b9c8c62
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A64: Add Disassemble method
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2018-01-28 18:03:57 +00:00 |
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MerryMage
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e0ab098473
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A32: data_processing: Remove !S assertions
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2018-01-28 12:59:52 +00:00 |
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MerryMage
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b96014b3b2
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A32: Implement BKPT
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2018-01-28 12:59:52 +00:00 |
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MerryMage
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14910e53d3
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A32: Add ExceptionRaised IR instruction and use it
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2018-01-28 12:59:52 +00:00 |
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Lioncash
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0216cbd2a5
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A64: Implement CRC32C
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2018-01-28 12:20:56 +00:00 |
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MerryMage
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2e14326fd5
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assert: Use fmt in ASSERT_MSG
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2018-01-28 00:00:58 +00:00 |
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MerryMage
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1f06ca80d4
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a64_emit_x64: Perform RSB predictions
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2018-01-27 22:48:08 +00:00 |
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MerryMage
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3f6889f700
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A32: Change UserCallbacks to be similar to A64's interface
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2018-01-27 22:45:48 +00:00 |
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Lioncash
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4798a40908
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reg_alloc: std::move RegAlloc's function argument
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2018-01-27 02:52:59 +00:00 |
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Lioncash
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c40e7acc8e
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General: Add missing override specifiers
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2018-01-27 02:46:04 +00:00 |
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MerryMage
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e111309aba
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EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128
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2018-01-27 02:00:49 +00:00 |
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MerryMage
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a1018a4eea
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a64_get_set_elimination_pass: Simplify algorithm
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2018-01-27 02:00:49 +00:00 |
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MerryMage
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ac1f4d3d5d
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a64_emit_x64: bug: x64 sign-extends 32-bit immediates
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2018-01-27 00:38:43 +00:00 |
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MerryMage
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9232be5553
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ir_opt: Add A64 Get/Set Elimination Pass
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2018-01-27 00:38:43 +00:00 |
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MerryMage
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39b7625e9d
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ir_emitter: Allow the insertion point for new instructions to be set
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2018-01-27 00:38:43 +00:00 |
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MerryMage
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68c5399607
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{a32,a64}_interface: Predict entrypoint
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2018-01-27 00:38:42 +00:00 |
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Lioncash
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dbddb4858a
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A64: Implement EXTR
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2018-01-26 22:07:48 +00:00 |
|
MerryMage
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bda9148e71
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A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
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2018-01-26 18:39:19 +00:00 |
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MerryMage
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e789d8ff53
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a64_jitstate: Have 128-bit wide spills
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2018-01-26 18:38:31 +00:00 |
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MerryMage
|
0c1c82a937
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IR: Implement IR instructions A64{Get,Set}S
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2018-01-26 18:38:30 +00:00 |
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MerryMage
|
ef6b4f20ca
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a64_emit_x64: Use xword from Xbyak::util
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2018-01-26 18:38:30 +00:00 |
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Lioncash
|
8c013e7928
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
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2018-01-26 17:06:48 +00:00 |
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Lioncash
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792cb91753
|
A64: Zero upper 64 bits in ORN if using the 64-bit variant
Resolves a TODO
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2018-01-26 17:06:26 +00:00 |
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MerryMage
|
a3af4dd218
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load_store_register_unprivileged: bug: LDTRSW
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2018-01-26 02:03:16 +00:00 |
|
MerryMage
|
06bea0ceaa
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A64: Implement CMEQ (register, vector)
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2018-01-26 01:52:42 +00:00 |
|
MerryMage
|
f7e8a2259a
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IR: Implement IR instructions VectorEqual{8,16,32,64,128}
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2018-01-26 01:52:06 +00:00 |
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