MerryMage
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3184edf4a9
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IR: Add IR instruction ZeroVector
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2018-02-20 15:41:07 +00:00 |
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MerryMage
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31f8fbc5b8
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emit_x64_floating_point: Add maybe_unused to preprocess parameter
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2018-02-20 15:41:07 +00:00 |
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MerryMage
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567eb1a2f1
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A64: Implement FMINNM (scalar)
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2018-02-20 14:14:40 +00:00 |
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MerryMage
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c6d8fa1d36
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A64: Implement FMAXNM (scalar)
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2018-02-20 14:05:14 +00:00 |
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MerryMage
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616056d9a3
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constant_pool: Add frame parameter
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2018-02-20 14:04:48 +00:00 |
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MerryMage
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a3747cb01c
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A64: Implement ADDP (scalar)
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2018-02-18 23:55:38 +00:00 |
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MerryMage
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5cd5d9f5f8
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reg_alloc: Only exchange GPRs
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2018-02-18 23:24:15 +00:00 |
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MerryMage
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dd0452a435
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A64: Implement DUP (element), scalar variant
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2018-02-18 18:58:01 +00:00 |
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MerryMage
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e5732ea66f
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emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
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2018-02-18 15:19:10 +00:00 |
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MerryMage
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40eb9c3253
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A64: Implement FMAX (scalar), FMIN (scalar)
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2018-02-18 13:49:23 +00:00 |
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MerryMage
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7cef39bdb4
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fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
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2018-02-18 13:47:41 +00:00 |
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MerryMage
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826dce212e
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travis: Switch unicorn repository
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2018-02-18 13:21:29 +00:00 |
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MerryMage
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9605f28792
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a64/config: Allow NaN emulation accuracy to be set
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2018-02-18 13:18:22 +00:00 |
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MerryMage
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e9435bc191
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a64_emit_x64: Add conf to A64EmitContext
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2018-02-18 13:18:22 +00:00 |
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MerryMage
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30b596df19
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fuzz_with_unicorn: Explicitly test floating point instructions
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2018-02-18 13:18:22 +00:00 |
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MerryMage
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be292a819c
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A64: Implement FSQRT (scalar)
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2018-02-18 13:18:22 +00:00 |
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MerryMage
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3c42d48a3f
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backend_x64: Accurately handle NaNs
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2018-02-18 13:18:22 +00:00 |
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MerryMage
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4aefed05d5
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fuzz_with_unicorn: Print AArch64 disassembly
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2018-02-18 13:18:22 +00:00 |
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MerryMage
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e585e1d49e
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T32: Add initial decoder list
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2018-02-14 19:29:19 +00:00 |
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MerryMage
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1598af4f12
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simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector)
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2018-02-13 19:01:47 +00:00 |
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MerryMage
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029ae11040
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A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero)
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2018-02-13 19:01:21 +00:00 |
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MerryMage
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91483ab975
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decoder/a64: Rearrange SIMD two-register misc decoders
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2018-02-13 18:51:43 +00:00 |
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MerryMage
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9158534048
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A64: Implement CMGE (register)
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2018-02-13 18:29:54 +00:00 |
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MerryMage
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41e421bf0b
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A64: Implement CMHI, CMHS
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2018-02-13 18:20:18 +00:00 |
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MerryMage
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324810cfad
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IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
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2018-02-13 18:20:00 +00:00 |
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MerryMage
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89007194a7
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A64: Implement SMAX, SMIN, UMAX, UMIN
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2018-02-13 17:57:07 +00:00 |
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MerryMage
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2880eb3da1
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IR: Implement Vector{Max,Min}{Signed,Unsigned}
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2018-02-13 17:56:46 +00:00 |
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MerryMage
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7d8543b70e
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A64: Implement CMGT (register)
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2018-02-13 15:47:52 +00:00 |
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MerryMage
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6d4f14e876
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IR: Implement VectorGreaterSigned
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2018-02-13 15:47:52 +00:00 |
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MerryMage
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9527d52c49
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Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
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2018-02-13 15:47:52 +00:00 |
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MerryMage
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182c776d7e
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a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning)
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2018-02-13 13:39:14 +00:00 |
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MerryMage
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229ff47738
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Merge branch 'feature/exclusive-mem'
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2018-02-13 12:53:29 +00:00 |
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MerryMage
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43f27b3e15
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A64: Implement STXP, STLXP, LDXP, LDAXP
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2018-02-13 12:50:50 +00:00 |
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MerryMage
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11eb8c2bea
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A64: Implement CLREX
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2018-02-13 12:31:16 +00:00 |
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MerryMage
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22285842af
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
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2018-02-13 12:30:58 +00:00 |
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MerryMage
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d7323d6799
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fuzz_with_unicorn: Speed up tests by not initializing/tearing down constantly
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2018-02-12 21:48:29 +00:00 |
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MerryMage
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eac0933738
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Merge branch 'feature/direct-page-table-access'
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2018-02-12 21:47:43 +00:00 |
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MerryMage
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49f1de3188
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Direct Page Table Access: Handle address spaces less than the full 64-bit in size
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2018-02-12 21:26:23 +00:00 |
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MerryMage
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406725e533
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Implement direct page table access
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2018-02-12 20:51:03 +00:00 |
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MerryMage
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adc2d5a3cc
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fuzz_with_unicorn: Fix read-past-end access via jit_iter
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2018-02-12 20:51:03 +00:00 |
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MerryMage
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885e092f99
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callbacks: Member functions should be const
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2018-02-12 20:51:03 +00:00 |
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MerryMage
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9598bd45ef
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a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
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2018-02-12 18:26:08 +00:00 |
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MerryMage
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276326e0e8
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abi: Add RAX to ABI_ALL_CALLER_SAVE
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2018-02-12 18:17:39 +00:00 |
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MerryMage
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7a161ed35c
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A64: Partially implement MRS
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2018-02-12 00:06:44 +00:00 |
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MerryMage
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b733479b5e
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A64: Implement DSB, DMB
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2018-02-11 23:27:28 +00:00 |
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MerryMage
|
1ba2642742
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Implement DC instructions
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2018-02-11 23:12:28 +00:00 |
|
Lioncash
|
e12fa19142
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A64: Implement NOT (vector)
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2018-02-11 20:14:03 +00:00 |
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MerryMage
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1b836b6deb
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IR: Implement FPMax, FPMin
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2018-02-11 16:43:47 +00:00 |
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MerryMage
|
94115d1775
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A64: Implement FADD (vector), vector variant
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2018-02-11 16:30:03 +00:00 |
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MerryMage
|
24def19cd7
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IR: Implement FPVectorAdd
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2018-02-11 16:29:48 +00:00 |
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