MerryMage
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7ec12cbade
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IR: Vector instructions now take esize argument in emitter
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2018-02-10 10:18:10 +00:00 |
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MerryMage
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b219105b75
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A64: Implement SIMD instruction SHL
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2018-02-10 09:49:55 +00:00 |
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MerryMage
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570911e693
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IR: Implement VectorLogicalShiftLeft{8,16,32,64}
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2018-02-10 09:31:54 +00:00 |
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MerryMage
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e03a9fed98
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opcodes: Sort vector IR opcodes alphabetically
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2018-02-10 09:15:01 +00:00 |
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MerryMage
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406c071008
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block_of_code: Increase constant pool size
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2018-02-09 16:04:56 +00:00 |
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MerryMage
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9be412bbc2
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devirtualize: MinGW uses Intanium MFP ABI
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2018-02-09 16:04:48 +00:00 |
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MerryMage
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7a0fdf01bb
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callback: Properly handle calls with return pointers and simplify interface
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2018-02-09 16:02:57 +00:00 |
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FernandoS27
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dee211c4df
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Implemented BSL, BIC, BIT and BIF vector instructions
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2018-02-09 13:28:16 +00:00 |
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MerryMage
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15da38d3aa
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devirtualize: Handle Windows ABI
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2018-02-09 11:19:40 +00:00 |
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MerryMage
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41ae12263d
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travis: Switch to yuzu-emu's unicorn repository
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2018-02-08 19:48:04 +00:00 |
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MerryMage
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83a762eee7
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fuzz_arm: Use SCOPE_FAIL
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2018-02-08 02:14:42 +00:00 |
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MerryMage
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b0991ee46f
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A32/decoder/arm: bug: Correct bitstring for SRS
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2018-02-08 02:05:49 +00:00 |
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MerryMage
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43035fd064
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devirtualize: Devirtualize Itanium ABI MFPs at runtime
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2018-02-07 12:25:45 +00:00 |
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MerryMage
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36ec1d09cf
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cast_util: Add BitCast and BitCastPointee
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2018-02-07 12:25:45 +00:00 |
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Lioncash
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1ee5b2e352
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A64: Move SDIV and UDIV out of data_processing_multiply.cpp
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2018-02-07 12:07:09 +00:00 |
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Lioncash
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25e7c94995
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A64: Implement ZIP1
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2018-02-07 12:06:49 +00:00 |
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FernandoS27
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c882e6819d
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Implemented UMULH and SMULH instructions
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2018-02-06 23:59:24 +00:00 |
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MerryMage
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32be42c68e
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A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
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2018-02-06 23:29:18 +00:00 |
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MerryMage
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b6775f1282
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impl: Add AdvSIMDExpandImm
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2018-02-06 23:04:23 +00:00 |
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MerryMage
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023c2c9818
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A64: Implement SUB (vector), scalar variant
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2018-02-06 22:12:39 +00:00 |
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MerryMage
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b544b8f4b1
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A64: Implement ADD (vector), scalar variant
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2018-02-06 22:09:39 +00:00 |
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MerryMage
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63d3a1cc1c
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A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
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2018-02-06 18:30:36 +00:00 |
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MerryMage
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59a84ed966
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A64: Implement BIC (vector, register)
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2018-02-06 17:57:50 +00:00 |
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MerryMage
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41bbb56cff
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docs: Update documentation (2018-02-05)
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2018-02-05 22:36:03 +00:00 |
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MerryMage
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8530f52729
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A64: Implement FMOV (general)
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2018-02-05 21:44:20 +00:00 |
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MerryMage
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ef9057555b
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translate/impl: Add Vpart
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2018-02-05 21:43:58 +00:00 |
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MerryMage
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37b4840c6f
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A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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2018-02-05 15:41:41 +00:00 |
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MerryMage
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a785d4fa66
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A64: Implement FCCMPE
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2018-02-05 12:26:19 +00:00 |
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MerryMage
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d2a2562a25
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A64: Implement FCCMP
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2018-02-05 12:26:19 +00:00 |
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MerryMage
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24178131a6
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a64_jitstate: Remove unnecessary FPSCR_nzcv member
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2018-02-05 12:26:19 +00:00 |
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MerryMage
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37a9472f81
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2018-02-05 12:26:19 +00:00 |
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Lioncash
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d86b8fc40d
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A64: Implement FMOV (register)
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2018-02-05 09:34:47 +00:00 |
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MerryMage
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97a742a7c0
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A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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2018-02-05 01:12:19 +00:00 |
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Lioncash
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e619902ee5
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A64: Implement CCMP (immediate)
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2018-02-05 00:45:39 +00:00 |
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Lioncash
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d91989a014
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A64: Implement CCMN (immediate)
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2018-02-05 00:45:39 +00:00 |
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Lioncash
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d5e58ac771
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A64: Implement CCMP (register)
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2018-02-05 00:45:39 +00:00 |
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Lioncash
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cd3113c208
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microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement
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2018-02-05 00:45:11 +00:00 |
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MerryMage
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10594c7adb
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A64: Implement CCMN (register)
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2018-02-04 23:11:07 +00:00 |
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MerryMage
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ee8726a8ba
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IR: Add ConditionalSelectNZCV instruction
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2018-02-04 23:08:43 +00:00 |
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Lioncash
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1621741fc6
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inst_gen: Make invalid_instructions a static inline variable
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2018-02-04 19:44:29 +00:00 |
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Lioncash
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73ad0b0b00
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fuzz_with_unicorn: Move instruction generator vector into GenRandomInst
Keeps scope localized and prevents potential static initialization issues.
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2018-02-04 19:44:29 +00:00 |
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MerryMage
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c3d2edf8ee
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A64: Implement FNEG
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2018-02-04 13:44:33 +00:00 |
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MerryMage
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ad5fe6dc43
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A64: Implement FABS
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2018-02-04 13:43:47 +00:00 |
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MerryMage
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107bd14a43
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A64: Implement FCSEL
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2018-02-04 13:40:37 +00:00 |
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MerryMage
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9db02bb4db
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A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
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2018-02-04 13:21:31 +00:00 |
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MerryMage
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f87ecad5a4
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A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2018-02-04 13:09:57 +00:00 |
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MerryMage
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cc7b315268
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backend_x64: Simplify FPDoubleToU32 and FPSingleToU32
They're inaccurate in terms of FPSR at the moment anyway.
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2018-02-04 13:07:19 +00:00 |
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MerryMage
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e5ce22aabc
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A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
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2018-02-04 12:49:40 +00:00 |
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Lioncash
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dc9317f714
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Common: Put AES code within its own nested namespace
Prevents the functions from potentially clashing with other stuff in Common in the future
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2018-02-03 23:11:46 +00:00 |
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Lioncash
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ccf9493653
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A64: Implement AESD
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2018-02-03 23:11:46 +00:00 |
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