MerryMage
7f3a790de5
fixup: travis: Test with disabled CPU feature detection
2018-01-24 19:42:54 +00:00
Lioncash
850337e434
CMakeLists: Add opcodes.inc to the source file list
...
Allows the file to show up nicely within IDEs
2018-01-24 19:42:02 +00:00
MerryMage
7d389fb5f8
travis: Test with disabled CPU feature detection
...
Ensure that fallbacks are working correctly.
2018-01-24 19:22:45 +00:00
MerryMage
314e020992
IR: Add IR instruction VectorZeroUpper
2018-01-24 17:11:13 +00:00
MerryMage
8ce3e0518a
a64_emit_x64: bug: EmitA64WriteMemory128 should write not read
2018-01-24 17:10:44 +00:00
FernandoS27
d1664096f5
Implemented SDIV and UDIV instructions
2018-01-24 17:09:00 +00:00
MerryMage
8873d17db2
A64: Implement LDR/STR (immediate, SIMD&FP)
2018-01-24 16:28:18 +00:00
MerryMage
7f5ce36368
IR: Add IR instructions A64Memory{Read,Write}128
...
Add the Windows ABI implementation
2018-01-24 16:28:18 +00:00
MerryMage
d6589fe3ee
IR: Add IR instructions A64Memory{Read,Write}128
...
This implementation only works on macOS and Linux.
2018-01-24 16:18:58 +00:00
MerryMage
5421c90216
IR: Add IR instruction VectorGetElement{8,16,32,64}
2018-01-24 16:18:58 +00:00
MerryMage
3932d6d695
IR: Add IR instruction ZeroExtendToQuad
2018-01-24 16:18:58 +00:00
MerryMage
264c446e54
block_of_code: Add ABI_RETURN2
2018-01-24 16:18:58 +00:00
MerryMage
ed63cc7ae9
interface: Move Vector typedef to config.h
2018-01-24 16:18:58 +00:00
MerryMage
ef81c2bcfc
bit_util: bug: Infinite loop in HighestSetBit
2018-01-24 16:18:58 +00:00
MerryMage
1db423b2ad
A64: Implement DUP (general)
2018-01-24 12:01:26 +00:00
MerryMage
6f1c44e311
IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
2018-01-24 12:01:26 +00:00
Lioncash
cdb588dab5
General: Default constructors and destructors where applicable
2018-01-24 09:07:22 +00:00
Lioncash
e300f1de46
ir_emitter: Remove unused includes
2018-01-24 01:50:10 +00:00
Lioncash
0e5988258d
A64: Implement RBIT
2018-01-24 01:49:58 +00:00
MerryMage
ae603909d6
ir_emitted: Remove unimplemented IR instruction Unimplemented
2018-01-23 22:16:15 +00:00
MerryMage
f014a5bec7
emit_x64: Extract BlockRangeInformation, remove template parameter
2018-01-23 19:44:35 +00:00
MerryMage
5f5e664a66
emit_x64: Use JitStateInfo
2018-01-23 19:44:35 +00:00
MerryMage
d52cb2d0de
A64: Implement CLS
...
This is not the cleanest implementation.
2018-01-23 19:44:35 +00:00
MerryMage
24383e543b
A64: Implement ADDP (vector)
2018-01-23 17:46:28 +00:00
MerryMage
dfcbe5bd2f
IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
2018-01-23 17:46:28 +00:00
MerryMage
961e64dfaf
backend_x64: Split emit_x64
2018-01-23 17:46:28 +00:00
MerryMage
41d9a6421d
fuzz_with_unicorn: Compare vectors
2018-01-23 17:46:28 +00:00
MerryMage
2b59e2ba0b
microinstruction: bug: Add missing opcodes
2018-01-23 17:46:28 +00:00
Lioncash
bd00d9bc80
A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL
2018-01-23 16:08:05 +00:00
Lioncash
768e5bcf9c
A64: Implement MADD and MSUB
2018-01-23 16:08:05 +00:00
Lioncash
ffaf837e58
A64: Implement CLZ
2018-01-23 11:55:09 +00:00
Lioncash
585e77d20e
opcodes: Add 64-bit CountLeadingZeroes opcode
2018-01-23 11:55:09 +00:00
MerryMage
f2dc9c7727
data_processing_register: Clean-up
2018-01-22 22:47:01 +00:00
Lioncash
efa67caf5f
A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL
...
Truly the most difficult A64 instructions to implement.
2018-01-22 11:54:12 +00:00
Lioncash
692cd6f27b
A64: Implement ASRV, LSLV, LSRV, and RORV
2018-01-22 11:51:46 +00:00
Lioncash
a5978a01ca
data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG
2018-01-21 23:33:18 +00:00
Lioncash
48e4e021f7
a32/a64_emit_x64: Remove unused includes
2018-01-21 20:09:23 +00:00
MerryMage
a6d17e6bb0
A64: Implement AND (vector)
2018-01-21 18:27:06 +00:00
MerryMage
9634532822
tests/A64: Randomize vectors
2018-01-21 17:56:27 +00:00
MerryMage
adcd34fac7
tests/A64/unicorn: Print interrupt number when InterruptHook is hit
2018-01-21 17:56:27 +00:00
MerryMage
304c91abd3
tests/A64: Allow RunTestInstance to start from an arbitrary offset
2018-01-21 17:56:27 +00:00
MerryMage
d333b5dcee
A64: Implement ADD (vector, vector)
2018-01-21 17:56:27 +00:00
Thomas Guillemard
1cf87a24b2
A64: Implement REV, REV32, and REV16 ( #126 )
2018-01-21 12:17:47 +00:00
MerryMage
9fc1570788
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128
...
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
2018-01-19 01:09:46 +00:00
MerryMage
50c18181aa
reg_alloc: GetBitWidth: Add UNREACHABLE
2018-01-18 23:46:01 +00:00
MerryMage
adccbf3c6b
reg_alloc: Consider bitwidth of data and registers when emitting instructions
2018-01-18 13:00:16 +00:00
MerryMage
7b7f239831
A64: Implement CSEL
2018-01-18 11:41:27 +00:00
MerryMage
2f84137f5b
IR: Implement Conditional Select
2018-01-18 11:36:52 +00:00
MerryMage
ebb3e80129
A64/tests: Split unicorn sanity checking from other tests
2018-01-17 20:00:42 +00:00
MerryMage
5740a0272c
tests/A64: Single random instruction: Test branch instructions as well
2018-01-17 00:35:01 +00:00
