MerryMage
21fb1c3a7f
emit_x64_floating_point: Reduce NaN processing overhead
2018-08-02 17:17:23 +01:00
MerryMage
f5c9f0fa5f
A64: Implement FMULX, scalar single/double variant
2018-08-02 14:11:30 +01:00
MerryMage
8f4777338e
IR: Implement FPMulX IR instruction
2018-08-02 14:11:14 +01:00
MerryMage
79e6440ea0
fuzz_with_unicorn: Randomize SP
2018-08-01 15:30:59 +01:00
MerryMage
33c80e3181
fuzz_with_unicorn: Randomize PC
2018-08-01 15:30:59 +01:00
MerryMage
8d41024661
testenv: Make code_mem mobile
2018-08-01 15:30:59 +01:00
Lioncash
a9fae0e610
emit_x64_vector: Vectorize 32-bit variants of paired min/max
...
Gets rid of the fallbacks for these cases.
2018-08-01 12:20:01 +01:00
MerryMage
8926a92a03
emit_x64_vector: Improve code emission of VectorGetElement* for index == 0
2018-07-31 22:04:11 +01:00
MerryMage
e20bd387e9
reg_alloc: Do a UseScratch if a Use destination is too small
2018-07-31 21:55:14 +01:00
MerryMage
a19fa0e294
fuzz_with_unicorn: Randomize FPCR.AHP and FPCR.FZ16
2018-07-31 21:27:24 +01:00
MerryMage
775f368205
emit_x64_floating_point: AVX implementation of ForceToDefaultNaN
2018-07-31 21:22:01 +01:00
MerryMage
71018a1faa
emit_x64_vector_floating_point: Prefer blendvp{s,d} to vblendvp{s,d} where possible
...
It's a cheaper instruction.
2018-07-31 21:13:16 +01:00
MerryMage
137f4b3b01
backend_x64: Remove all use of xmm0
2018-07-31 20:54:16 +01:00
MerryMage
e73d67a841
emit_x64_vector_floating_point: AVX implementation of ForceToDefaultNaN
2018-07-31 20:33:50 +01:00
MerryMage
43cca54dd3
emit_x64_vector_floating_point: Reduce codesize of ForceToDefaultNaN
2018-07-31 20:25:56 +01:00
MerryMage
5dc40f49f8
emit_x64_vector_floating_point: Reduce codesize of EmitTwoOpVectorOperation
2018-07-31 20:25:03 +01:00
MerryMage
07622eedf0
emit_x64_vector_floating_point: Correct FMA in FTZ mode
...
x64 rounds before flushing to zero
AArch64 rounds after flushing to zero
This difference of behaviour is noticable if something would round to a smallest normalized number
2018-07-31 18:12:39 +01:00
MerryMage
621c85b90c
emit_x64_floating_point: DenormalsAreZero is redundant as hardware already does DAZ
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Exceptions: F{MIN,MAX}{,NM}
2018-07-31 18:05:13 +01:00
MerryMage
3d0ebaa6d6
emit_x64_floating_point: FlushToZero is redundant as hardware already does FTZ
2018-07-31 16:08:13 +01:00
MerryMage
f626ff82d0
backend_x64: Fix FPVectorMulAdd and FPMulAdd NaN handling with denormals
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Denormals should be treated as zero in NaN handler
2018-07-31 16:07:46 +01:00
MerryMage
adeb9d9ba0
a32/fuzz_arm: Disable vfp tests
2018-07-31 16:01:28 +01:00
MerryMage
19ea70d3a0
fuzz_with_unicorn: Randomize FPCR.FZ
2018-07-31 15:39:39 +01:00
MerryMage
895db36543
backend_x64: Fix bugs when FPCR.FZ=1
...
Bugs:
* DenormalsAreZero flushed to positive zero instead of preserving sign.
* FMAXNM/FMINNM (scalar) should perform DAZ *before* special zero handling.
* FMAX/FMIN/FMAXNM/FMINNM (vector) did not DAZ.
2018-07-31 15:39:33 +01:00
MerryMage
d7e2de2659
fuzz_with_unicorn: Extract RandomFpcr function
...
Deduplicate randomization of fpcr and make use of FP::FPCR
2018-07-31 12:35:04 +01:00
MerryMage
c858d6c7b4
fp/info: Deduplicate functions
2018-07-30 20:25:29 +01:00
MerryMage
5b88ec252c
emit_x64_floating_point: Deduplicate EmitFPMulAdd implementation
2018-07-30 20:16:45 +01:00
MerryMage
73d3efc3e0
emit_x64_floating_point: Deduplicate code
2018-07-30 15:13:43 +01:00
MerryMage
c9508c3d13
fuzz_with_unicorn: Randomize FPCR.DN
2018-07-30 14:52:22 +01:00
MerryMage
29708331bb
emit_x64_vector_floating_point: Fix FPVector{Max,Min} when FPCR.DN = 1
2018-07-30 14:52:22 +01:00
MerryMage
150764f718
emit_x64_floating_point: Fix FP{Max,Min} when FPCR.DN = 1
2018-07-30 14:52:22 +01:00
MerryMage
b7d209cfa4
IR: SSE4.1 implementation of FPVectorRoundInt
2018-07-30 14:52:22 +01:00
MerryMage
8cf8270139
A64: Implement FRINT{N,M,P,Z,A,X,I} (vector), single/double variant
2018-07-30 13:32:20 +01:00
MerryMage
8f46c26d26
IR: Initial implementation of FPVectorRoundInt
2018-07-30 13:31:51 +01:00
MerryMage
97017bbdf7
A64: Implement SQADD and SQSUB, scalar variant
2018-07-30 11:01:38 +01:00
MerryMage
ce58863903
IR: Generalise SignedSaturated{Add,Sub} to support more bitwidths
2018-07-30 11:01:36 +01:00
MerryMage
e80f8ff244
a64_emit_x64: Bugfix EmitA64OrQC - Incorrect argument
2018-07-30 11:00:37 +01:00
Lioncash
1e4ec7e1f0
simd_three_same: Extract non-paired SMAX, SMIN, UMAX, UMIN code to a common function
...
Deduplicates a bit of code and makes its layout consistent with the
paired variants
2018-07-30 08:40:32 +01:00
Lioncash
6f9dc9b143
A64: Implement SMAXP, SMINP, UMAXP, UMINP
2018-07-30 08:40:32 +01:00
Lioncash
1dfb29fc14
ir: Add opcodes for vector paired maximum and minimums
...
For the time being, we can just do a naive implementation which avoids
falling back to the interpreter a bit. Horizontal operations aren't
necessarily x86 SIMD's forte anyways.
2018-07-30 08:40:32 +01:00
Lioncash
017b51095f
A64: Implement SMAXV, SMINV, UMAXV, and UMINV
2018-07-30 08:39:33 +01:00
Lioncash
aae22eec26
ir: Add opcodes for performing scalar integral min/max
2018-07-30 08:39:33 +01:00
Lioncash
6ef3af3bc9
A64: Implement PMULL{2}
2018-07-29 10:04:58 +01:00
Lioncash
2a4ce19af3
translate: Deduplicate GetDataSize() functions
...
Avoids defining the same function multiple times in different files.
2018-07-29 10:00:34 +01:00
Lioncash
0e015008af
floating_point_{conditional}_compare: Deduplicate code
...
Deduplicates the implementation code of instructions by extracting the
code to a common function.
2018-07-29 10:00:34 +01:00
MerryMage
259237ce58
common: Move all cryptographic function to common/crypto
2018-07-29 08:49:12 +01:00
MerryMage
c5f1080b40
a32_emit_x64: BMI2 implementation of A32SetCpsr
2018-07-27 11:41:31 +01:00
MerryMage
a23304a16c
a32_emit_x64: Shorten EmitA32GetCpsr
2018-07-27 11:24:06 +01:00
MerryMage
57604d2ea8
a32_emit_x64: Assert that memory layout assumption in EmitA32GetCpsr is valid
2018-07-26 19:26:01 +01:00
Lioncash
945fa48667
A64: Implement PMUL
2018-07-26 16:16:30 +01:00
Lioncash
656a4042a2
ir: Add opcode for performing polynomial multiplication
2018-07-26 16:16:30 +01:00
