MerryMage
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023c2c9818
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A64: Implement SUB (vector), scalar variant
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2018-02-06 22:12:39 +00:00 |
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MerryMage
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b544b8f4b1
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A64: Implement ADD (vector), scalar variant
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2018-02-06 22:09:39 +00:00 |
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MerryMage
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63d3a1cc1c
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A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
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2018-02-06 18:30:36 +00:00 |
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MerryMage
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59a84ed966
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A64: Implement BIC (vector, register)
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2018-02-06 17:57:50 +00:00 |
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MerryMage
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41bbb56cff
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docs: Update documentation (2018-02-05)
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2018-02-05 22:36:03 +00:00 |
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MerryMage
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8530f52729
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A64: Implement FMOV (general)
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2018-02-05 21:44:20 +00:00 |
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MerryMage
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ef9057555b
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translate/impl: Add Vpart
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2018-02-05 21:43:58 +00:00 |
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MerryMage
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37b4840c6f
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A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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2018-02-05 15:41:41 +00:00 |
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MerryMage
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a785d4fa66
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A64: Implement FCCMPE
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2018-02-05 12:26:19 +00:00 |
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MerryMage
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d2a2562a25
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A64: Implement FCCMP
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2018-02-05 12:26:19 +00:00 |
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MerryMage
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24178131a6
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a64_jitstate: Remove unnecessary FPSCR_nzcv member
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2018-02-05 12:26:19 +00:00 |
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MerryMage
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37a9472f81
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2018-02-05 12:26:19 +00:00 |
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Lioncash
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d86b8fc40d
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A64: Implement FMOV (register)
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2018-02-05 09:34:47 +00:00 |
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MerryMage
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97a742a7c0
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A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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2018-02-05 01:12:19 +00:00 |
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Lioncash
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e619902ee5
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A64: Implement CCMP (immediate)
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2018-02-05 00:45:39 +00:00 |
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Lioncash
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d91989a014
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A64: Implement CCMN (immediate)
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2018-02-05 00:45:39 +00:00 |
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Lioncash
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d5e58ac771
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A64: Implement CCMP (register)
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2018-02-05 00:45:39 +00:00 |
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Lioncash
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cd3113c208
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microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement
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2018-02-05 00:45:11 +00:00 |
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MerryMage
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10594c7adb
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A64: Implement CCMN (register)
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2018-02-04 23:11:07 +00:00 |
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MerryMage
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ee8726a8ba
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IR: Add ConditionalSelectNZCV instruction
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2018-02-04 23:08:43 +00:00 |
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Lioncash
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1621741fc6
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inst_gen: Make invalid_instructions a static inline variable
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2018-02-04 19:44:29 +00:00 |
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Lioncash
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73ad0b0b00
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fuzz_with_unicorn: Move instruction generator vector into GenRandomInst
Keeps scope localized and prevents potential static initialization issues.
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2018-02-04 19:44:29 +00:00 |
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MerryMage
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c3d2edf8ee
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A64: Implement FNEG
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2018-02-04 13:44:33 +00:00 |
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MerryMage
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ad5fe6dc43
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A64: Implement FABS
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2018-02-04 13:43:47 +00:00 |
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MerryMage
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107bd14a43
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A64: Implement FCSEL
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2018-02-04 13:40:37 +00:00 |
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MerryMage
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9db02bb4db
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A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
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2018-02-04 13:21:31 +00:00 |
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MerryMage
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f87ecad5a4
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A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2018-02-04 13:09:57 +00:00 |
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MerryMage
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cc7b315268
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backend_x64: Simplify FPDoubleToU32 and FPSingleToU32
They're inaccurate in terms of FPSR at the moment anyway.
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2018-02-04 13:07:19 +00:00 |
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MerryMage
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e5ce22aabc
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A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
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2018-02-04 12:49:40 +00:00 |
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Lioncash
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dc9317f714
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Common: Put AES code within its own nested namespace
Prevents the functions from potentially clashing with other stuff in Common in the future
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2018-02-03 23:11:46 +00:00 |
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Lioncash
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ccf9493653
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A64: Implement AESD
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2018-02-03 23:11:46 +00:00 |
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Lioncash
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33bc59c55a
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A64: Implement AESE
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2018-02-03 23:11:46 +00:00 |
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MerryMage
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db6999fc38
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backend_x64: Use a reference to BlockOfCode instead of a pointer
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2018-02-03 14:28:57 +00:00 |
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MerryMage
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a7209dc2f7
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IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
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2018-02-03 13:41:36 +00:00 |
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MerryMage
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2262b08a04
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A64: Implement INS (general)
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2018-02-03 13:07:00 +00:00 |
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MerryMage
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3c140141db
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A64: Implement INS (element)
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2018-02-03 13:03:50 +00:00 |
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MerryMage
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af5fb0a1a0
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A64: Implement SMOV
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2018-02-03 12:58:19 +00:00 |
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MerryMage
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818b9a4673
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A64: Implement UMOV
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2018-02-03 12:55:53 +00:00 |
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MerryMage
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9ea219e010
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basic_block: Fix bogus GCC maybe-uninitialized warning
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2018-02-03 03:04:44 +00:00 |
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MerryMage
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64e37de179
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A64: Implement FCVT
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2018-02-03 01:23:11 +00:00 |
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MerryMage
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f1d2cdde34
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fuzz_with_unicorn: Skip instructions that need to be interpreted
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2018-02-03 01:22:40 +00:00 |
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MerryMage
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2fd70e56ce
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A64: Implement FMOV (scalar, immediate)
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2018-02-03 00:52:48 +00:00 |
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MerryMage
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567c1b57fc
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A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
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2018-02-02 22:39:24 +00:00 |
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MerryMage
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c42ca435ba
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A64: Implement FCMP, FCMPE
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2018-02-02 22:25:51 +00:00 |
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MerryMage
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0131a87c43
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a64_jitstate: A64 does not have a seperate FPSCR.NZCV
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2018-02-02 22:25:18 +00:00 |
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MerryMage
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4728257d4e
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A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
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2018-02-02 22:04:09 +00:00 |
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MerryMage
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fcabd95ad0
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IR: Merge U32 and U64 variants of FP instructions
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2018-02-02 21:55:23 +00:00 |
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MerryMage
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6d9adb668e
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A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2018-02-02 21:10:30 +00:00 |
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MerryMage
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bfeb9ff617
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emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1
This bug wasn't discovered earlier because we previously only used index == 0.
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2018-02-02 21:07:00 +00:00 |
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MerryMage
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cc40b83ed0
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IR: Implement VectorSetElement{8,16,32,64}
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2018-02-02 21:00:12 +00:00 |
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