MerryMage
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78c640ad9e
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A64: Implement FMLS (vector), single/double variant
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2018-07-25 13:45:02 +01:00 |
|
MerryMage
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b6b6993884
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emit_x64_vector_floating_point: Specify NanHandler::function_type explicitly
MSVC doesn't like dealing with auto return types
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2018-07-25 13:38:32 +01:00 |
|
MerryMage
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4b9d12a585
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emit_x64_vector_floating_point: ChooseOnFsize arguments maybe_unused
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2018-07-25 13:27:31 +01:00 |
|
MerryMage
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b1e3616de2
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IR: Implement FPVectorNeg
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2018-07-25 13:25:35 +01:00 |
|
MerryMage
|
4343612ec4
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A64: Implement FMLA (vector), single/double variant
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2018-07-25 13:20:07 +01:00 |
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MerryMage
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93eeb25fac
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IR: Implement FPVectorMulAdd
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2018-07-25 13:19:48 +01:00 |
|
MerryMage
|
57e5c7e7a5
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emit_x64_vector_floating_point: Standardize naming scheme
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2018-07-25 12:08:00 +01:00 |
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MerryMage
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bcb9e4106d
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emit_x64_floating_point: Simplify indexers
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2018-07-25 12:05:41 +01:00 |
|
MerryMage
|
83aa5854b6
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emit_x64_vector_floating_point: Simplify EmitVectorOperation*
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2018-07-25 11:34:22 +01:00 |
|
MerryMage
|
f4087c81e5
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mp: rename mp.h to mp/function_info.h
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2018-07-25 11:28:36 +01:00 |
|
MerryMage
|
18640903ac
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emit_x64_vector: Slightly improve ArithmeticShiftRightByte
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2018-07-25 09:33:02 +01:00 |
|
MerryMage
|
e048441d44
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emit_x64_vector: Simplify VectorShuffleImpl
|
2018-07-24 22:46:45 +01:00 |
|
MerryMage
|
ff025e88d0
|
IR: Implement A64OrQC
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2018-07-24 19:04:40 +01:00 |
|
MerryMage
|
6fac68dd1d
|
A64: Implement UQSHRN, UQRSHRN (vector)
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2018-07-24 18:54:28 +01:00 |
|
MerryMage
|
5a8d9c3487
|
emit_x64_vector: -0x80000000 isn't -0x80000000
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2018-07-24 18:45:45 +01:00 |
|
MerryMage
|
759289ec5c
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A64: Implement UQXTN (vector)
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2018-07-24 18:31:32 +01:00 |
|
MerryMage
|
2a96281587
|
emit_x64_vector: Fix non-SSE4.1 saturated narrowing reconstruction comparison
Allows non-SSE4.1 to produce the correct FPSR.QC flag
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2018-07-24 18:17:14 +01:00 |
|
MerryMage
|
0682353626
|
A64: Implement SQXTN (vector)
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2018-07-24 17:59:14 +01:00 |
|
MerryMage
|
6c5229ed47
|
emit_x64_vector: packusdw reqiures SSE4.1
In EmitVectorSignedSaturatedNarrowToUnsigned32.
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2018-07-24 17:32:00 +01:00 |
|
MerryMage
|
158d9b16f0
|
A64: Implement SQSHRUN, SQRSHRUN (vector)
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2018-07-24 17:20:49 +01:00 |
|
MerryMage
|
f886013526
|
simd_shift_by_immediate: Simplify ShiftRight
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2018-07-24 16:38:51 +01:00 |
|
MerryMage
|
d9b59c69de
|
A64: Implement SQXTUN
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2018-07-24 16:32:10 +01:00 |
|
MerryMage
|
50fe28b976
|
microinstruction: Reorganize FPSCR related instruction queries
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2018-07-24 12:13:18 +01:00 |
|
Lioncash
|
d9d036acc9
|
microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR()
These were forgotten when the opcodes were added.
|
2018-07-24 11:55:15 +01:00 |
|
Lioncash
|
db96163637
|
u128: Make Bit() a const-qualified member function
This function doesn't modify the struct members, so it can be made
const.
|
2018-07-24 09:15:44 +01:00 |
|
MerryMage
|
f7052ae04d
|
A64: Implement FRSQRTS (vector), single/double variant
|
2018-07-23 22:58:52 +01:00 |
|
MerryMage
|
0925ef6248
|
A64: Implement FRSQRTE (vector), single/double variant
|
2018-07-23 22:46:12 +01:00 |
|
MerryMage
|
f4cbbe3218
|
A64: Implement FRSQRTS (scalar), single/double variant
|
2018-07-23 22:05:17 +01:00 |
|
MerryMage
|
4ef864e81c
|
IR: Implement FPRSqrtStepFused
|
2018-07-23 22:05:17 +01:00 |
|
MerryMage
|
9dffeebc44
|
fp: Implement FPRSqrtStepFused
|
2018-07-23 22:05:17 +01:00 |
|
MerryMage
|
aa0455667e
|
fp: Implement FPNeg
|
2018-07-23 22:03:07 +01:00 |
|
MerryMage
|
cbde1c5a15
|
process_nan: Add two operand variant
|
2018-07-23 22:03:07 +01:00 |
|
Lioncash
|
1ec2663de3
|
A64: Implement FMAXP, FMINP, FMAXNMP and FMINNMP's scalar double/single-precision variant
|
2018-07-23 21:22:32 +01:00 |
|
MerryMage
|
027ddf9e2c
|
emit_x64_floating_point: Fixup special NaN case in FMA FPMulAdd implementation
|
2018-07-23 21:10:52 +01:00 |
|
Lioncash
|
75a9f7799a
|
fp: Use a forward declaration in fused.h
It's permissible to forward declare here, so we can do so and eliminate
a direct header dependency
|
2018-07-23 20:46:34 +01:00 |
|
Lioncash
|
1ee16303bd
|
u128: Implement comparison operators in terms of one another
We can just implement the comparisons in terms of operator< and
implement inequality with the negation of operator==.
|
2018-07-23 20:23:10 +01:00 |
|
MerryMage
|
3b77f48a76
|
tests: Print cpu info
|
2018-07-23 20:22:38 +01:00 |
|
MerryMage
|
bed3cc03f9
|
u128: StickyLogicalShiftRight requires special-casing for amount == 64
In this case (128 - amount) == 64, and this invokes undefined behaviour
|
2018-07-23 20:22:01 +01:00 |
|
Lioncash
|
15d04f489b
|
A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant
|
2018-07-23 19:13:39 +01:00 |
|
Lioncash
|
7cfccdfa29
|
A64: Implement FMUL (by element)'s scalar double/single-precision variant
|
2018-07-23 19:13:39 +01:00 |
|
MerryMage
|
7d2d62ece7
|
emit_x64_floating_point: Implement accurate fallback for FPMulAdd{32,64}
|
2018-07-23 18:52:09 +01:00 |
|
MerryMage
|
a599eacebf
|
fp: Implement FPMulAdd
|
2018-07-23 18:52:07 +01:00 |
|
MerryMage
|
d70b90ed5d
|
process_nan: Add FPProcessNaNs3
|
2018-07-23 18:51:36 +01:00 |
|
MerryMage
|
38ef0e04cb
|
block_of_code: Add SysV ABI fifth and sixth parameters
|
2018-07-23 18:51:36 +01:00 |
|
MerryMage
|
8e2ff56569
|
u128: Add StickyLogicalShiftRight
|
2018-07-23 18:51:36 +01:00 |
|
MerryMage
|
3b337df076
|
u128: Add Multiply64To128
|
2018-07-23 18:51:36 +01:00 |
|
MerryMage
|
8219075ea3
|
u128: Add u128::Bit
|
2018-07-23 18:51:11 +01:00 |
|
MerryMage
|
a574dcb2ae
|
u128: Add comparison operators
|
2018-07-23 18:51:11 +01:00 |
|
MerryMage
|
391d6d46a4
|
unpacked: Use ResidualErrorOnRightShift in FPRoundBase
Fixes a bug relating to exponents that are severely out of range.
|
2018-07-23 18:29:44 +01:00 |
|
MerryMage
|
5e0cf9c83e
|
fp: Remove MantissaT
|
2018-07-23 14:23:47 +01:00 |
|