Lioncash
b0e1eb5a15
A64: Implement USQADD's scalar and vector variants
2018-09-09 17:06:03 +01:00
Lioncash
28424c7ad1
ir: Add opcodes form unsigned saturated accumulations of signed values
2018-09-09 17:06:03 +01:00
Lioncash
9923ea0b71
A64: Implement SUQADD's scalar and vector variants
2018-09-09 17:06:03 +01:00
Lioncash
4c0adbb7f1
ir: Add opcodes for signed saturated accumulations of unsigned values
2018-09-09 17:06:03 +01:00
Lioncash
799bfed2df
A64: Implement SMLAL{2}, SMLSL{2}, UMLAL{2}, and UMLSL{2}'s vector by-element variants
...
We can simply modify the general function made for SMULL{2} and
UMULL{2}'s by-element variants to also handle the other multiply-based
by-element variants.
2018-09-09 13:55:40 +01:00
Lioncash
94451ec321
A64: Implement UMULL{2}'s vector by-element variant
2018-09-09 13:55:40 +01:00
Lioncash
45867deac9
A64: Implement SMULL{2}'s vector by-element variant
2018-09-09 13:55:40 +01:00
Lioncash
02357939ac
ir/value: Replace includes with forward declarations
...
enum classes are still considered complete types when forward declared
(as the compiler knows the exact size of the type from the declaration
alone). The only difference in this case being that the members of the
enum class aren't visible. Given we don't use the members within this
header in any way, we can simply forward declare them here and remove
the inclusions.
2018-09-09 09:04:22 +01:00
Lioncash
450f721df5
ir/cond: Migrate to C++17 nested namespace specifiers
2018-09-09 09:03:42 +01:00
Lioncash
d20e7694dd
A64: Implement URSQRTE
2018-09-09 00:37:28 +01:00
Lioncash
4f3bde5f12
ir: Add opcodes for performing unsigned reciprocal square root estimates
2018-09-09 00:37:28 +01:00
Lioncash
cfeeaec1c6
A64: Implement URECPE
2018-09-09 00:37:28 +01:00
Lioncash
622b60efd6
ir: Add opcodes for unsigned reciprocal estimate
2018-09-09 00:37:28 +01:00
Lioncash
b575b23ea9
A64: Implement SQNEG's scalar and vector variant
2018-09-08 11:23:32 +01:00
Lioncash
06062a91c5
A64: Add opcodes for signed saturating negations
2018-09-08 11:23:32 +01:00
Lioncash
8b13421bac
A64: Implement SQDMULH's by-element scalar variant
2018-09-08 11:23:32 +01:00
Lioncash
9122a6e19e
A64: Implement SQDMULH's by-element vector variant
2018-09-08 11:23:32 +01:00
MerryMage
959446573f
A64: Implement FastDispatchHint
2018-09-07 22:07:44 +01:00
MerryMage
2be95f2b3b
A32: Implement FastDispatchHint
2018-09-07 22:07:44 +01:00
MerryMage
96f23acd00
ir/terminal: Add FastDispatchHint
2018-09-07 21:29:47 +01:00
Lioncash
f5ca9e9e4a
A64: Implement SQDMULH's scalar variant
2018-09-06 20:35:43 +01:00
Lioncash
af8bea59d5
ir: Add opcodes for scalar signed saturated doubling multiplies
2018-09-06 20:35:43 +01:00
Lioncash
fed4220dc0
A64: Implement SQDMULH's vector variant
2018-09-06 20:35:43 +01:00
Lioncash
72eb6ad362
ir: Add opcodes for signed saturated doubling multiplies
2018-09-06 20:35:43 +01:00
Lioncash
235165ba70
A64: Implement SQABS' scalar variant
2018-09-06 15:49:25 +01:00
Lioncash
1adca93d4a
A64: Implement SQABS' vector variant.
2018-09-06 15:49:25 +01:00
Lioncash
f978c445fa
ir: Add opcodes for signed saturated absolute values
2018-09-06 15:49:25 +01:00
MerryMage
e987a84062
IR: Simplify FP{Single,Double}ToFixed{U,S}{32,64}
2018-09-05 21:04:40 +01:00
Lioncash
a0c587ac1a
A32/decoder: Add missing <algorithm> includes
...
These includes should be present, as we use std::find_if() within these headers.
2018-09-03 13:53:26 +01:00
Lioncash
799e519707
ir_emitter: Rename fpscr_controlled parameters to fpcr_controlled
...
Part of addressing #333
2018-08-28 18:43:01 +01:00
MerryMage
68ca03e8d4
a32/exception_generating: BPKT: Define unpredictable behaviour
...
Define unpredictable behaviour to be BKPT executes conditionally
2018-08-26 00:48:29 +01:00
MerryMage
42c0589881
A32: Add define_unpredictable_behaviour option
2018-08-26 00:48:27 +01:00
MerryMage
3262736fb6
A32/location_descriptor: Change formatting to use hex
2018-08-26 00:33:44 +01:00
MerryMage
f3bb54e042
microinstruction: A32ExceptionRaised causes CPU exception
2018-08-26 00:33:43 +01:00
MerryMage
2b4224bcb4
A32/types: CondToString: Add nv
2018-08-25 23:02:58 +01:00
MerryMage
72ed55f143
a32_emit_x64: Fix incorrect BMI2 implementation for SetCpsr
...
* The MSB for each byte in cpsr_ge were not being appropriately set.
* We also expand test coverage to test this case.
* We fix the disassembly of the MSR (imm) and MSR (reg) instructions as well.
2018-08-23 14:48:23 +01:00
MerryMage
deb1ab62d4
A64/translate: Standardize arguments of helper functions
...
Don't pass in IREmitter when TranslatorVisitor is already available.
2018-08-21 12:26:46 +01:00
MerryMage
30b6a5ffca
A64/translate: Standardize TranslatorVisitor abbreviation
...
Prefer v to tv.
2018-08-21 12:16:32 +01:00
Lioncash
a42f301c28
A64: Implement SQXTN, SQXTUN, and UQXTN's scalar variants
...
We can implement these in terms of the vector variants
2018-08-20 08:08:57 +01:00
Lioncash
8a822def14
A64: Implement SDOT and UDOT's (by element) variants
...
Gets all of the dot product instructions out of the way.
2018-08-20 08:06:59 +01:00
MerryMage
bc6cf3021f
A64: Implement TBL and TBX
2018-08-18 22:00:03 +01:00
MerryMage
8067ab9553
IR: Add VectorTable and VectorTableLookup IR instructions
2018-08-18 21:59:44 +01:00
MerryMage
0e0e839ba0
opcodes: Cleanup opcodes table
...
* Remove T:: prefix from types.
* Add another column for a 4th argument.
2018-08-18 19:39:59 +01:00
Lioncash
8e47d44c4d
A64: Implement SDOT and UDOT's vector variant
2018-08-18 15:19:39 +01:00
Lioncash
3a367f341f
A64: Implement SADALP and UADALP
...
While we're at it we can join the code for SADDLP and UADDLP with these
instructions, since the only difference is we do an accumulate at the
end of the operation.
2018-08-18 14:24:43 +01:00
Lioncash
5f322a160f
A64: Implement SRSHL and URSHL
...
Implements both scalar and vector variants.
2018-08-18 14:23:29 +01:00
Lioncash
a278775c43
ir: Add opcodes for performing rounding left shifts
2018-08-18 14:23:29 +01:00
Lioncash
fc96d512c9
A64: Implement ISB
...
Given we want to ensure that all instructions are fetched again, we can
treat an ISB instruction as a code cache flush.
2018-08-18 13:30:54 +01:00
Lioncash
2a0317198f
A64: Implement FCVTN{2}
2018-08-16 23:01:38 +01:00
Lioncash
f9e084283b
A64: Implement FCVTL{2}
2018-08-16 23:01:38 +01:00
