MerryMage
adccbf3c6b
reg_alloc: Consider bitwidth of data and registers when emitting instructions
2018-01-18 13:00:16 +00:00
MerryMage
7b7f239831
A64: Implement CSEL
2018-01-18 11:41:27 +00:00
MerryMage
2f84137f5b
IR: Implement Conditional Select
2018-01-18 11:36:52 +00:00
MerryMage
0892b487b7
A64/translate/branch: bug: Read-after-write error in BLR
2018-01-17 00:34:33 +00:00
MerryMage
e77bc26945
A64: Implement SBFM, BFM, UBFM
2018-01-17 00:15:44 +00:00
MerryMage
0c37ca71c6
A64: Implement MOVN, MOVZ, MOVK
2018-01-15 21:47:28 +00:00
MerryMage
a04ca20a89
ir/location_descriptor: Add missing <functional> header for std::hash
2018-01-14 20:23:24 +00:00
MerryMage
bc73004dd5
a64_merge_interpret_blocks: Remove debug output
2018-01-13 22:05:05 +00:00
MerryMage
fd9530be25
A64: Optimization: Merge interpret blocks
2018-01-13 21:57:18 +00:00
MerryMage
5218ad97e2
A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate
2018-01-13 18:06:06 +00:00
MerryMage
b1a8c39c19
A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31
2018-01-13 18:06:06 +00:00
MerryMage
64827fbe8e
a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers
2018-01-13 18:06:06 +00:00
MerryMage
1bfa04d7ac
emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64
2018-01-13 18:06:06 +00:00
MerryMage
9ab130490b
A64: Add ExceptionRaised IR instruction
...
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
2018-01-13 18:06:06 +00:00
MerryMage
7438d07f2b
A64/translate: Add TranslateSingleInstruction function
2018-01-12 19:34:25 +00:00
MerryMage
83afe4353c
Misc. fixups of MSVC build
2018-01-12 18:13:53 +00:00
MerryMage
ad95a75047
imm: Suppress MSVC warning C4244: value will never be truncated
2018-01-12 17:18:07 +00:00
MerryMage
ebaeceec37
fixup! imm: compiler bug: MSVC 19.12
2018-01-12 17:11:42 +00:00
MerryMage
3a0b7d59f0
imm: compiler bug: MSVC 19.12 with /permissive- flag doesn't support fold expressions
2018-01-12 17:01:21 +00:00
MerryMage
dd285abec5
A64/decoder: Split decoder data from header
2018-01-11 13:03:56 +00:00
MerryMage
30af089e49
ir_opt: Split off A32 specific passes
2018-01-11 13:03:56 +00:00
MerryMage
648212995c
A64: Implement LDP, STP
2018-01-11 13:03:54 +00:00
MerryMage
192e7a73ea
A64/location_descriptor: Fix -fpermissive warning on GCC
2018-01-10 18:56:12 +00:00
MerryMage
89bdade0a0
A64: Implement LDP, STP
2018-01-10 02:05:08 +00:00
MerryMage
16e50ca0db
A32: Implement load stores (immediate)
2018-01-10 01:30:30 +00:00
MerryMage
a5caa7cd8d
A64: Implement SVC
2018-01-09 21:30:13 +00:00
MerryMage
79091043f0
imm: bug: SignExtend wasn't working for T with bit size > 32
2018-01-09 21:22:17 +00:00
MerryMage
78ffd3da90
a64_emit_x64: Don't use far code for now
2018-01-09 21:21:50 +00:00
MerryMage
347a5c7171
EmitA64SetW: bug: should zero extend to entire 64-bit register
2018-01-09 21:21:15 +00:00
MerryMage
cc647ce869
EmitA64SetNZCV: bug: to_store is scratch
2018-01-09 21:20:55 +00:00
MerryMage
c029aef4da
emit_x86: Fix nzcv for EmitSub
2018-01-09 18:57:07 +00:00
MerryMage
f19f014a42
A64: Implement SVC
2018-01-09 18:57:07 +00:00
MerryMage
1aa4afaa22
a64_emit_x64: Call interpreter
2018-01-09 18:57:07 +00:00
MerryMage
6633a19d65
A64: Add batch register retrieval to interface
2018-01-09 18:57:06 +00:00
MerryMage
305456b407
A64: Implement compare and branch
2018-01-09 18:57:06 +00:00
MerryMage
08c25c9ae7
A64: PSTATE access and tests
2018-01-09 18:57:06 +00:00
MerryMage
c4abd1fda1
A64: Implement branch (register)
2018-01-09 18:57:06 +00:00
MerryMage
5497fe9056
A64: Implement branch
2018-01-09 18:57:06 +00:00
MerryMage
f3e763a667
A64: Implement logical
2018-01-09 18:57:06 +00:00
MerryMage
f0c29feddb
A64: Implement pcrel
2018-01-09 18:57:06 +00:00
MerryMage
8a8dcad250
A64: Implement addsub instructions
2018-01-09 18:57:06 +00:00
MerryMage
1431cedcaa
A64: Implement ADD_shifted
2018-01-09 18:57:06 +00:00
MerryMage
ef6fd92fed
A64: Backend framework
2018-01-09 18:57:06 +00:00
MerryMage
557fe60164
A64: Initial framework
2018-01-09 18:57:06 +00:00
MerryMage
512dae0361
IR: Compile-time type-checking of IR
2018-01-09 18:20:57 +00:00
MerryMage
b88b7ecbbf
IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg
2018-01-09 18:20:57 +00:00
MerryMage
dbbbf4c331
Make IR->A32 LocationDescriptor conversion explicit
2018-01-09 18:20:57 +00:00
MerryMage
be094ff150
Final A32 refactor
2018-01-09 18:20:57 +00:00
MerryMage
faf64f4a5f
EmitX64: JitState type as template parameter
2018-01-09 18:20:57 +00:00
MerryMage
d95a01bcb3
Package up emit context
2018-01-09 18:20:57 +00:00
