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Author SHA1 Message Date
MerryMage
909e9aae2e fp: Implement FPProcessException 2018-07-15 14:32:06 +01:00
MerryMage
f6cdd58976 fp: Move fp_util to fp/util 2018-07-15 14:32:06 +01:00
MerryMage
60f5ef3a11 fp: Add FPSR 2018-07-15 14:32:06 +01:00
MerryMage
2384b7e6a0 fp: Add FPInfo 
Provides information about floating-point format for various bit sizes
 2018-07-15 14:32:06 +01:00
MerryMage
af82bc4871 safe_ops: Implement safe shifting operations 
Implement shifiting operations that perform consistently across architectures
without running into undefined or implemented-defined behaviour.
 2018-07-15 14:32:06 +01:00
MerryMage
a3a8efb018 bit_util: Implement MostSignificantBit 2018-07-15 14:32:06 +01:00
MerryMage
3f2194dcba bit_util: Use Ones to implement Bits 2018-07-15 14:32:06 +01:00
MerryMage
c319c4a193 bit_util: Add ClearBit and ModifyBit 2018-07-15 14:32:06 +01:00
MerryMage
639b0bb493 u128: Implement u128 
For when we need a 128-bit integer
 2018-07-15 14:32:06 +01:00
Lioncash
6c6cdcec10 A64: Implement UCVTF (vector, integer)'s double/single-precision variant 2018-07-15 12:46:35 +01:00
Lioncash
d921423160 ir: Add opcodes for vector conversion of u32/u64 to floating-point 2018-07-15 12:46:35 +01:00
Lioncash
8754289927 simd_three_different: Deduplicate common implementations 
Generally, the only difference between the signed variants and the
unsigned variants is whether or not we use a sign-extension or
zero-extension, so we can simply use common functions to implement both
cases without totally duplicating code twice here.
 2018-07-15 12:44:49 +01:00
Lioncash
c396261092 floating_point_conversion_integer: Handle S64/U64 -> F32 conversions in SCVTF_float_int and UCVTF_float_int 2018-07-15 12:29:26 +01:00
Lioncash
0b2c6c4eb8 ir: Add opcodes for converting S64 and U64 to single-precision floating-point values 2018-07-15 12:29:26 +01:00
Lioncash
1dc24b6d2e constant_pool: Remove unnecessary std::memset from constructor 
AllocateFromCodeSpace() already zeroes out the allocated memory.
 2018-07-15 12:12:28 +01:00
MerryMage
9dd908de1d fuzz_with_unicorn: Avoid self-modifying code 
* Don't immediately terminate when unicorn raises an interrupt
* Detect self-modifying code
 2018-07-15 12:07:52 +01:00
MerryMage
b81a9a52e1 fuzz_with_unicorn: Configure as per qemu max configuration 2018-07-14 08:51:08 +01:00
Lioncash
751bc31b60 tests/A32/testenv: Add type aliases for register arrays 
Allows avoiding duplicating std::array instance sizes and types.
 2018-07-14 08:22:18 +01:00
Lioncash
badc29f2ea tests/unicorn: Add type aliases to the Unicorn class 
Centralizes all register and vector array definitions to a single set of
aliases, so if these are ever changed, then the rest of the testing code
will follow suit without the need to manually change them.
 2018-07-14 08:22:18 +01:00
Lioncash
ca7a35f55f A64: Implement ADDV 2018-07-14 08:18:51 +01:00
Lioncash
5b5d79144e emit_x64_vector: Vectorize fallback path for EmitVectorMaxU32() 2018-07-14 08:17:46 +01:00
Lioncash
563959908b simd_three_same: Join FPAbsoluteComparison() into FPCompareRegister() 
These are part of the same comparison family, so there's no real point
in keeping them separate.
 2018-07-14 07:50:37 +01:00
Lioncash
7391f70318 A64: Implement scalar double/single-precision variants of FACGE, FACGT, FCMEQ, FCMGE, FCMGT 2018-07-14 07:50:37 +01:00
MerryMage
dbfdb2506a emit_x64_floating_point: Fix EmitFPU64ToDouble for TowardsMinusInfinity rounding mode 2018-07-14 07:11:32 +01:00
MerryMage
e292ac2e7b backend_x86: Add FPSCR_RMode to EmitContext 2018-07-14 07:11:32 +01:00
MerryMage
22cd3bac86 tests/A64: Randomize FPCR.RMode for single random instruction 2018-07-14 07:11:32 +01:00
MerryMage
c277e6f988 fp: Extract common RoundingMode enum 2018-07-14 07:11:32 +01:00
Lioncash
1bfac4aed0 inst_gen: Compress loop into std::any_of in IsInvalidInstruction() 
Same behavior, but using a more self-documenting function.
 2018-07-13 18:28:38 +01:00
Lioncash
a665470545 fuzz_with_unicorn: Move std::vector outside loop in small random block test case 
Avoids constructing and destructing the vector repeatedly, we can just
alter the contents of the vector on each iteration instead. Also move
out the std::array instances as well, like with the floating-point test
case and the single random instruction test case.

We can also use the regular form of std::generate and avoid hardcoding
size values twice.
 2018-07-13 14:48:09 +01:00
MerryMage
537df2e0b8 fuzz_with_unicorn: Temporarily disable FDIV 2018-07-12 22:34:58 +01:00
MerryMage
28786e6ee2 tests/A64: Test small blocks 2018-07-12 22:34:58 +01:00
MerryMage
fc5870d592 fuzz_with_unicorn: Randomize FPCR.RMode 2018-07-12 13:52:29 +01:00
Lioncash
d2406bf42b floating_point_conversion_integer: Use FPS64ToDouble and FPU64ToDouble in SCVTF_float_int and UCVTF_float_int 
The opcodes introduced in 979b6f39f1621b80bd463645ec5b08661cb6b1bf can
also be used here, avoiding more falling back to the interpreter.
 2018-07-10 00:27:10 +01:00
Lioncash
6fc9e127fe simd_scalar_two_register_misc: Handle 64-bit case in SCVTF and UCVTF's scalar double/single-precision variant 
Avoids falling back to the interpreter in the 64-bit case.
 2018-07-10 00:15:19 +01:00
Lioncash
08572fa670 emit_x64_floating_point: Correct use of UseGpr() in EmitFPU32ToDouble() and EmitFPU32ToSingle() 
In the non-AVX512 path, the following code is present:

code.mov(from.cvt32(), from.cvt32());

since this potentially modifies 'from', we should be using
UseScratchGpr() instead.
 2018-07-10 00:15:19 +01:00
Lioncash
c121a7c611 emit_x64_floating_point: Add AVX512F conversion operations to EmitFPU32ToSingle() and EmitFPU32ToDouble() 
AVX-512F provides convenient instructions for these kinds of conversions
directly
 2018-07-10 00:15:19 +01:00
Lioncash
979b6f39f1 ir: Add opcodes for converting S64 and U64 to double-precision values 2018-07-10 00:15:19 +01:00
MerryMage
5573953428 Merge branch 'global_monitor' 2018-07-07 22:52:50 +01:00
Lioncash
0ae8540234 simd_two_register_misc: Utilize FPVectorAbs in FABS implementations 
Since we already have opcodes introduced to implement FACGE and FACGT,
we can reutilize it for the FABS implementations.
 2018-07-07 21:42:42 +01:00
Lioncash
c566307b87 ir: Extend FPVectorAbs opcode to also handle 16-bit elements for FP16 2018-07-07 21:42:42 +01:00
Lioncash
9760ea1f93 A64: Implement FACGE's vector single/double precision variants 2018-07-07 14:49:47 +01:00
Lioncash
488ebdb793 A64: Implement FACGT's vector single/double precision variants 2018-07-07 14:49:47 +01:00
Lioncash
f769be89dc ir: Add opcodes for performing vector absolute floating-point values 
This will be usable for implementing FACGE and FACGT
 2018-07-07 14:49:47 +01:00
Lioncash
402032d107 emit_x64_vector: Deduplicate a bit of code in EmitVectorSetElement{8, 32, 64} functions 
Given both branches are the same, we can hoist out the common code.
 2018-07-07 14:49:14 +01:00
Lioncash
f7d11baa1c A64: Implement load/store single structure instructions 
Implements LD{1, 2, 3, 4}, LD{1, 2, 3, 4}R, and ST{1, 2, 3, 4} single
structure variants.
 2018-07-06 23:01:35 +01:00
Lioncash
c4be14d5bf emit_x64_vector: Deduplicate a bit of code within EmitVectorGetElement8() 
Given both branches use the same destination register size, we can hoist
the common code out.
 2018-07-06 23:00:58 +01:00
MerryMage
a6432b7e5b A64: Add ClearExclusiveState method 2018-07-04 00:05:14 +01:00
MerryMage
86cd8c9a69 tests: Add print_info program 
Eases debugging by printing out dynarmic IR for a given A64 instruction, along with
information about what instruction dynarmic thinks it is.

Also prints an LLVM disassembly of the instruction.
 2018-06-27 21:23:14 +01:00
MerryMage
f4e824d396 ir/basic_block: Add missing U16 immediate type to DumpBlock 2018-06-27 21:23:05 +01:00
MerryMage
89a2b80c1f llvm_disassemble: Allow disassembly of invalid AArch64 instructions 2018-06-27 21:22:53 +01:00