MerryMage
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9598bd45ef
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a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
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2018-02-12 18:26:08 +00:00 |
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MerryMage
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276326e0e8
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abi: Add RAX to ABI_ALL_CALLER_SAVE
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2018-02-12 18:17:39 +00:00 |
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MerryMage
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7a161ed35c
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A64: Partially implement MRS
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2018-02-12 00:06:44 +00:00 |
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MerryMage
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b733479b5e
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A64: Implement DSB, DMB
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2018-02-11 23:27:28 +00:00 |
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MerryMage
|
1ba2642742
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Implement DC instructions
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2018-02-11 23:12:28 +00:00 |
|
Lioncash
|
e12fa19142
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A64: Implement NOT (vector)
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2018-02-11 20:14:03 +00:00 |
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MerryMage
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1b836b6deb
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IR: Implement FPMax, FPMin
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2018-02-11 16:43:47 +00:00 |
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MerryMage
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94115d1775
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A64: Implement FADD (vector), vector variant
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2018-02-11 16:30:03 +00:00 |
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MerryMage
|
24def19cd7
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IR: Implement FPVectorAdd
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2018-02-11 16:29:48 +00:00 |
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MerryMage
|
9379d54a44
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A64: Implement SSHLL, SSHLL2
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2018-02-11 16:24:55 +00:00 |
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MerryMage
|
a7e4202828
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IR: Implement VectorSignExtend
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2018-02-11 16:24:33 +00:00 |
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MerryMage
|
01760f1a21
|
CMakeLists: Ignore warnings within xbyak
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2018-02-11 14:57:35 +00:00 |
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MerryMage
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ae7d118f22
|
A64: Implement DUP (element), vector variant
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2018-02-11 14:34:13 +00:00 |
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MerryMage
|
b87814ce88
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load_store_multiple_structures: Improve IR codegen for selem == 1 case
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2018-02-11 12:48:49 +00:00 |
|
MerryMage
|
6113346a5b
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A64: Implement FSUB (vector)
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2018-02-11 12:18:05 +00:00 |
|
MerryMage
|
8c6fce20d2
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IR: Implement FPVectorSub
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2018-02-11 12:17:53 +00:00 |
|
MerryMage
|
3fffeadf0d
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emit_x64_vector: EmitOneArgumentFallback
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2018-02-11 11:59:43 +00:00 |
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MerryMage
|
4df6c424df
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Forward declare IR::Opcode and IR::Type where possible
|
2018-02-11 11:52:44 +00:00 |
|
MerryMage
|
09632954d7
|
A64: Implement CNT
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2018-02-11 11:52:44 +00:00 |
|
MerryMage
|
c2c9ea85a5
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IR: Implement VectorPopulationCount
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2018-02-11 11:52:44 +00:00 |
|
MerryMage
|
0996d4fd2e
|
A64: Implement MLS (vector)
|
2018-02-11 11:04:46 +00:00 |
|
MerryMage
|
5319f6af95
|
A64: Implement MLA (vector)
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2018-02-11 11:00:16 +00:00 |
|
MerryMage
|
17519df3e8
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emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
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2018-02-11 10:47:22 +00:00 |
|
MerryMage
|
eac6a56a4b
|
emit_x64_vector: More explicit lambda decay
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2018-02-11 10:47:00 +00:00 |
|
MerryMage
|
727b1b0b51
|
A64: Implement MUL (vector)
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2018-02-11 10:18:47 +00:00 |
|
MerryMage
|
80fce9c4b9
|
IR: Implement VectorMultiply
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2018-02-11 10:18:29 +00:00 |
|
MerryMage
|
cb65a26da2
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emit_x64_vector: Order alphabetically
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2018-02-11 09:41:37 +00:00 |
|
MerryMage
|
2b968981a1
|
A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
|
2018-02-11 01:06:26 +00:00 |
|
MerryMage
|
7681159811
|
decoder/a64: Don't rearrange unrelated decoders
|
2018-02-11 00:43:33 +00:00 |
|
MerryMage
|
56fe848e4e
|
A64: Implement SUB (vector)
|
2018-02-10 23:58:33 +00:00 |
|
MerryMage
|
b429efa081
|
A64: Implement SIMD instruction SSRA, vector variant
|
2018-02-10 23:30:00 +00:00 |
|
MerryMage
|
0a96a437cb
|
A64: Implement SIMD instruction SSHR, vector variant
|
2018-02-10 23:28:05 +00:00 |
|
MerryMage
|
a5299d0be5
|
IR: Implement VectorArithmeticShiftRight
|
2018-02-10 23:27:46 +00:00 |
|
MerryMage
|
8e8068cfaf
|
impl: Improve Vpart setter
|
2018-02-10 17:05:52 +00:00 |
|
MerryMage
|
5ffa84f41d
|
A64: Implement SIMD instructions XTN, XTN2
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2018-02-10 17:01:33 +00:00 |
|
MerryMage
|
dc9785bdcd
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IR: Implement VectorNarrow
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2018-02-10 17:01:33 +00:00 |
|
MerryMage
|
ebc594385c
|
constant_pool: Allow for 128-bit constants
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2018-02-10 16:36:00 +00:00 |
|
MerryMage
|
8e23683b63
|
emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
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2018-02-10 16:24:43 +00:00 |
|
MerryMage
|
d9f803924e
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IR: Implement VectorSub
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2018-02-10 11:25:50 +00:00 |
|
MerryMage
|
c01bbbd09d
|
A64: Implement SIMD instruction USRA, vector variant
|
2018-02-10 11:12:54 +00:00 |
|
MerryMage
|
9e80f94b5f
|
A64: Implement SIMD instruction USHR, vector variant
|
2018-02-10 11:05:58 +00:00 |
|
MerryMage
|
e6a0a4d8ce
|
IR: Implement VectorLogicalShiftRight
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2018-02-10 11:05:22 +00:00 |
|
MerryMage
|
60ddaa8f38
|
A64: Implement SIMD instructions USHLL, USHLL2
|
2018-02-10 10:35:14 +00:00 |
|
MerryMage
|
670b47149e
|
IR: Implement VectorZeroExtend
|
2018-02-10 10:35:14 +00:00 |
|
MerryMage
|
7ec12cbade
|
IR: Vector instructions now take esize argument in emitter
|
2018-02-10 10:18:10 +00:00 |
|
MerryMage
|
b219105b75
|
A64: Implement SIMD instruction SHL
|
2018-02-10 09:49:55 +00:00 |
|
MerryMage
|
570911e693
|
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
|
2018-02-10 09:31:54 +00:00 |
|
MerryMage
|
e03a9fed98
|
opcodes: Sort vector IR opcodes alphabetically
|
2018-02-10 09:15:01 +00:00 |
|
MerryMage
|
406c071008
|
block_of_code: Increase constant pool size
|
2018-02-09 16:04:56 +00:00 |
|
MerryMage
|
9be412bbc2
|
devirtualize: MinGW uses Intanium MFP ABI
|
2018-02-09 16:04:48 +00:00 |
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