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Author SHA1 Message Date
Lioncash
f4a1196e60 emit_x64_vector: Simplify EmitVectorLogicalShiftRight8() 
We can generate the mask and AND it against the result of a halfword
shift instead of looping.
 2018-08-31 19:44:54 +01:00
Lioncash
4fc51f41b1 emit_x64_vector: Amend value definition in SSE 4.1 path for EmitVectorSignExtend16() 
We should be defining the value after the results have been calculated
to be consistent with the rest of the code.
 2018-08-31 13:48:32 +01:00
Lioncash
e50adae441 emit_x64_vector: Remove fallback in EmitVectorSignExtend64() 
This is fairly trivial to do manually.
 2018-08-31 13:48:14 +01:00
Lioncash
0a364f385d emit_x64_vector: Remove fallback for EmitVectorSignExtend32() 
We can just do the extension manually, which gets rid of the need to
fall back here.
 2018-08-31 13:48:14 +01:00
Lioncash
799e519707 ir_emitter: Rename fpscr_controlled parameters to fpcr_controlled 
Part of addressing #333
 2018-08-28 18:43:01 +01:00
MerryMage
68ca03e8d4 a32/exception_generating: BPKT: Define unpredictable behaviour 
Define unpredictable behaviour to be BKPT executes conditionally
 2018-08-26 00:48:29 +01:00
MerryMage
42c0589881 A32: Add define_unpredictable_behaviour option 2018-08-26 00:48:27 +01:00
MerryMage
3262736fb6 A32/location_descriptor: Change formatting to use hex 2018-08-26 00:33:44 +01:00
MerryMage
f3bb54e042 microinstruction: A32ExceptionRaised causes CPU exception 2018-08-26 00:33:43 +01:00
MerryMage
2b4224bcb4 A32/types: CondToString: Add nv 2018-08-25 23:02:58 +01:00
MerryMage
0d17b076bd block_of_code: Hide NX support behind compiler flag 
Systems that require W^X can use the DYNARMIC_ENABLE_NO_EXECUTE_SUPPORT cmake option.
 2018-08-23 20:56:05 +01:00
MerryMage
1ee3f3d9e6 Implement perfmap 2018-08-23 15:09:19 +01:00
MerryMage
72ed55f143 a32_emit_x64: Fix incorrect BMI2 implementation for SetCpsr 
* The MSB for each byte in cpsr_ge were not being appropriately set.
* We also expand test coverage to test this case.
* We fix the disassembly of the MSR (imm) and MSR (reg) instructions as well.
 2018-08-23 14:48:23 +01:00
MerryMage
2a705d0393 backend/x64: Support W^X systems 
Closes #176.
 2018-08-22 13:21:23 +01:00
BreadFish64
c95f023403 Backend: Create "backend" folder 
similar to the "frontend" folder
 2018-08-22 13:13:46 +01:00
MerryMage
deb1ab62d4 A64/translate: Standardize arguments of helper functions 
Don't pass in IREmitter when TranslatorVisitor is already available.
 2018-08-21 12:26:46 +01:00
MerryMage
30b6a5ffca A64/translate: Standardize TranslatorVisitor abbreviation 
Prefer v to tv.
 2018-08-21 12:16:32 +01:00
MerryMage
f9cd96bb1a emit_x64_vector: Avoid recalculating addresses in EmitVectorTableLookup 2018-08-21 12:16:32 +01:00
Lioncash
a42f301c28 A64: Implement SQXTN, SQXTUN, and UQXTN's scalar variants 
We can implement these in terms of the vector variants
 2018-08-20 08:08:57 +01:00
Lioncash
8a822def14 A64: Implement SDOT and UDOT's (by element) variants 
Gets all of the dot product instructions out of the way.
 2018-08-20 08:06:59 +01:00
MerryMage
b604f0d237 emit_x64_vector: Don't load zero constant from memory in EmitVectorTableLookup 2018-08-19 21:33:33 +01:00
MerryMage
8ac462fca9 emit_x64_vector: Special-case is_defaults_zero && table_size == 2 in EmitVectorTableLookup 2018-08-19 21:32:54 +01:00
MerryMage
08fae72a57 emit_x64_vector: Release registers when possible in EmitVectorTableLookup 2018-08-19 21:08:00 +01:00
MerryMage
c7d264bbe2 reg_alloc: Add the ability to Release an allocation early 2018-08-19 21:07:37 +01:00
MerryMage
3172a4b066 emit_x64_vector: Special-case table_size == 1 in EmitVectorTableLookup 2018-08-19 09:29:41 +01:00
MerryMage
50c589b2b5 emit_x64_vector: SSE4.1 implementation of EmitVectorTableLookup 2018-08-18 22:07:58 +01:00
MerryMage
bc6cf3021f A64: Implement TBL and TBX 2018-08-18 22:00:03 +01:00
MerryMage
8067ab9553 IR: Add VectorTable and VectorTableLookup IR instructions 2018-08-18 21:59:44 +01:00
MerryMage
0e0e839ba0 opcodes: Cleanup opcodes table 
* Remove T:: prefix from types.
* Add another column for a 4th argument.
 2018-08-18 19:39:59 +01:00
Lioncash
8e47d44c4d A64: Implement SDOT and UDOT's vector variant 2018-08-18 15:19:39 +01:00
Lioncash
3a367f341f A64: Implement SADALP and UADALP 
While we're at it we can join the code for SADDLP and UADDLP with these
instructions, since the only difference is we do an accumulate at the
end of the operation.
 2018-08-18 14:24:43 +01:00
Lioncash
5f322a160f A64: Implement SRSHL and URSHL 
Implements both scalar and vector variants.
 2018-08-18 14:23:29 +01:00
Lioncash
a278775c43 ir: Add opcodes for performing rounding left shifts 2018-08-18 14:23:29 +01:00
MerryMage
720efe337e emit_x64_floating_point: Fix smallest normal check in EmitFPMulAdd 2018-08-18 13:49:19 +01:00
Lioncash
fc96d512c9 A64: Implement ISB 
Given we want to ensure that all instructions are fetched again, we can
treat an ISB instruction as a code cache flush.
 2018-08-18 13:30:54 +01:00
Lioncash
2a0317198f A64: Implement FCVTN{2} 2018-08-16 23:01:38 +01:00
Lioncash
f9e084283b A64: Implement FCVTL{2} 2018-08-16 23:01:38 +01:00
Lioncash
9f873410c8 A64: Implement FMAXNM and FMINNM vector variants. 
Currently we can implement these in terms of the scalar IR variants.
 2018-08-16 23:00:42 +01:00
Lioncash
d5d2c36221 A64: Implement FMAXP, FMAXNMP, FMINP, and FMINNMP's vector variants 
We can just implement these in terms of scalars for the time being.
 2018-08-16 15:12:43 +01:00
MerryMage
1474f09d1c emit_x64_vector_floating_point: Correct value of smallest_normal_number 2018-08-16 10:55:02 +01:00
MerryMage
821cabac1b fp/info: Incorrect point_position in FPValue 2018-08-16 10:50:28 +01:00
MerryMage
550d662f0e load_store_exclusive: Define s == t state to be Constraint_NONE 
Downstream (yuzu) mentioned that the instruction:

STXR W9, W9, [X0]

was executed in the program "Crash N-Sane Trilogy".
 2018-08-16 10:04:54 +01:00
MerryMage
0b69381ff4 A64/translate: Allow for unpredictable behaviour to be defined 2018-08-16 09:59:06 +01:00
MerryMage
6d236d459f system: Implement MRS CNTFRQ_EL0 2018-08-16 09:58:34 +01:00
MerryMage
6cbb6fb190 A32/testenv: Add missing headers 2018-08-15 13:48:50 +01:00
MerryMage
67293289bf externals: Update xbyak to v5.67 
Merge commit '1812bd20d08020bfff2ca15e23c0377a21e3cee0'
 2018-08-15 13:31:03 +01:00
MerryMage
1812bd20d0 Squashed 'externals/xbyak/' changes from 2794cde7..671fc805 
671fc805 update test/cybozu
8ca86231 remove mutable in Address
8b93498f add cmpsb/scasb/...
7eb62750 avoid core_sharing_data_cache = 0 for some cloud envrionment
85767e95 support mingw64
59573e6e add PROTECT_RE mode for protect()
71b75f65 fix push(qword[mem])
811f4959 Merge branch 'rsdubtso-master'
8e3cb711 Account for potentially zero 0xb leaf when parsing cache/topology via cpuid
a816249f update version
fe083912 fix to avoid zero division for some virtual machine
f0a8f7fa update version
cac09b7a Merge pull request #62 from mgouicem/master
1f96b5e0 Fixes an error raised by clang < 3.9
c0f885ac Merge pull request #61 from mgouicem/master
bfe2d201 Change default value for n_cores in setCacheHierarchy.
fd587b55 change format and add getter for data_cache_size
80b3c7b9 remove macro
88189609 Merge branch 'mgouicem-master'
e6b79723 Adding queries to get the cpu topology on Intel architectures.
221384f0 vmov* supports [mem]|k|z
c04141ef define XBYAK_NO_OP_NAMES for test
af7f05ee add const for Label

git-subtree-dir: externals/xbyak
git-subtree-split: 671fc805d09d075f48d4625f183ef2e1ef725106
 2018-08-15 13:28:55 +01:00
MerryMage
9a9580290b externals: Document subtrees 2018-08-15 13:28:13 +01:00
Lioncash
714a8405bc A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants 
Currently we implement these in terms of the scalar variants. Falling
back to the interpreter is slow enough to make it more effective than
doing that.
 2018-08-14 08:48:06 +01:00
Lioncash
8cab459661 A64: Implement UQADD/UQSUB's scalar variants 2018-08-14 08:48:06 +01:00