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1194 Commits

Author SHA1 Message Date
MerryMage
8219075ea3 u128: Add u128::Bit 2018-07-23 18:51:11 +01:00
MerryMage
a574dcb2ae u128: Add comparison operators 2018-07-23 18:51:11 +01:00
MerryMage
391d6d46a4 unpacked: Use ResidualErrorOnRightShift in FPRoundBase 
Fixes a bug relating to exponents that are severely out of range.
 2018-07-23 18:29:44 +01:00
MerryMage
5e0cf9c83e fp: Remove MantissaT 2018-07-23 14:23:47 +01:00
MerryMage
8c0a84cbd3 FPRSqrtEstimate: Improve documentation of RecipSqrtEstimate 2018-07-23 11:26:51 +01:00
Lioncash
c41d8552a7 FPRSqrtEstimate: Deduplicate array bounds 
Dehardcodes a few constants in the loops.
 2018-07-23 10:56:46 +01:00
Lioncash
4cf055ba47 A64: Implement FMAXV, FMINV, FMAXNMV, and FMINNMV 2018-07-23 10:45:12 +01:00
Lioncash
bf24f0febf FPRSqrtEstimate: Use forward declarations where applicable 2018-07-23 10:36:49 +01:00
Lioncash
206230e9c4 translate: Return by bool in helpers where applicable 
Gets rid of a bit of duplication regarding the early-out cases and makes
all helpers functions consistent (previously some had a return type of
bool, while others had a return type of void).
 2018-07-23 10:36:28 +01:00
Lioncash
346b725878 Simplify fallback case for EmitVectorSetElement64() 2018-07-23 10:34:44 +01:00
MerryMage
2c34e1d964 emit_x64_floating_point: s/Esimate/Estimate/ 2018-07-22 21:49:08 +01:00
MerryMage
5213fb670d simd_scalar_two_register_misc: Implement FRSQRTE, scalar variant 2018-07-22 18:35:43 +01:00
MerryMage
7ed089fd8e IR: Implement FPRSqrtEstimate 2018-07-22 18:35:43 +01:00
MerryMage
cd2e286313 simd_vector_x_indexed_element: Implement FMUL (by element), vector variant 2018-07-22 17:43:08 +01:00
MerryMage
fc6b73bd85 a64_emit_x64: Ensure host has updated ticks in EmitA64GetCNTPCT 
Discovered by @Subv.
Fixes incomplete fix begun in 5a91c94dca47c9702dee20fbd5ae1f4c07eef9df.
That fix fails to take into account that LinkBlock doesn't update ticks until there
are no remaining ticks to be executed.

Test added to confirm fix.
 2018-07-22 16:16:26 +01:00
MerryMage
888c6783a1 a64_emit_x64: Fix stack misalignment on Windows for 128-bit exclusive writes 
Discovered by @Subv.
Includes a test to ensure this codepath is exercised on Windows.
 2018-07-22 15:26:25 +01:00
Lioncash
352d53908a emit_x64_aes: Eliminate extraneous usage of a scratch register in EmitAESInverseMixColumns() 
We can just use the same register the data is in as the result register,
eliminating the need to use a completely separate register to store the
result.
 2018-07-22 07:06:09 +01:00
Lioncash
ab7fe77799 A64: Implement SADDLV 2018-07-22 07:05:36 +01:00
Lioncash
09bd2b2c6e A64: Implement UADDLV 2018-07-22 07:05:36 +01:00
Lioncash
62e86d7287 fp: Use forward declarations where applicable 
Minimizes the amount of files that need to be rebuilt if the headers
ever change.
 2018-07-22 07:04:47 +01:00
Lioncash
b3edb7a956 emit_x64_vector: Append 'v' prefix onto movq in AVX path 
This is something I missed when adding in the AVX broadcast code.
 2018-07-22 07:04:35 +01:00
Subv
7ea1241953 A64: The A64SetTPIDR IR instruction writes to a system register and should not be eliminated by the dead code elimination pass. 
Previously this instruction was alway eliminated, resulting in incorrect values for TPIDR_EL0.
 2018-07-21 09:34:23 +01:00
MerryMage
853bdd6b98 fp: A64::FPCR -> FP::FPCR 2018-07-20 11:39:39 +01:00
MerryMage
faa3ea2f2a bit_util: Implement ClearBits and ModifyBits 2018-07-20 11:39:30 +01:00
MerryMage
f659f0fb5c system: Simplify static_cast 2018-07-19 12:03:23 +01:00
MerryMage
5a91c94dca system: Ensure value of CNTPCT_EL0 is accurate 
Since we currently only update the host's tick count at the end of a
block, we force an end-of-block before executing a MRS %, CNTPCT_ELO
instruction.
 2018-07-19 02:37:28 +01:00
Lioncash
1e303aa1f3 safe_ops: Avoid cases where shift bases are invalid with signed values 
For example, say the converted signed type is s64, shifting left  by 63
bits would be undefined behavior.

However, given an ASL is essentially the same behavior as an LSL
we can just use an unsigned type instead of converting to a signed type.
 2018-07-17 21:24:34 +01:00
Lioncash
e3d533d954 safe_ops: Avoid signed overflow in Negate() 
Negation of values such as -9223372036854775808 can't be represented in
signed equivalents (such as long long), leading to signed overflow.
Therefore, we can just invert bits and add 1 to perform this behavior
with unsigned arithmetic.
 2018-07-17 21:24:34 +01:00
Lioncash
6bf7280179 simd_scalar_shift_by_immediate: Implement FCVT{ZS, ZU} (vector, fixed-point)'s scalar double/single-precision variant 2018-07-17 19:45:58 +01:00
Lioncash
be860cf7e1 simd_scalar_two_register_misc: Implement FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU} (vector)'s scalar double/single-precision variants 
We can simply implement this in terms of the fixed-point IR opcodes.
 2018-07-17 19:45:58 +01:00
Lioncash
adbb8964c6 emit_x64: Remove FPSCR_RoundTowardsZero() virtual function from EmitContext struct 
This code was bugged in that we were comparing if the rounding mode was
not equal to rounding towards zero. Fortunately, however, nothing uses
this function anymore, and there's already the more general
FPSCR_RMode() available, so this can be removed entirely.
 2018-07-17 19:27:33 +01:00
Lioncash
6bcc766729 emit_x64: Add missing <array> include 
Commit 755adef62e504a8d616de9dda8937d2428a9471b introduced a helper
alias for std::array, eliminating the need to manually type out sizes
for them, however I forgot to add the include for <array>
 2018-07-17 19:00:00 +01:00
Lioncash
755adef62e emit_x64_vector{_floating_point}: Add helper alias for sizing arrays relative to vector width 
Avoids needing to remember to specify the proper size of the arrays, all
that's needed is to specify the type of the array and the size will
automatically be deduced from it. This helps prevent potential oversized
or undersized arrays from being specified.
 2018-07-17 17:54:22 +01:00
MerryMage
0c3b6bd11f A64/PopRSBHint: Prevent RETing to a guest PC of ~0ull from crashing the jit 2018-07-16 18:29:25 +01:00
MerryMage
39958434b6 A64: Implement FABD in terms of existing IR instructions 
Fixes NaN issue. Closes #306.
 2018-07-16 16:51:16 +01:00
MerryMage
4a3453179b FPRoundInt: Final FPRound based on new sign 
While this shouldn't change any of the results in theory, it's just logically more consistent
 2018-07-16 15:07:26 +01:00
MerryMage
5879b5f73f emit_x64_floating_point: SSE4.1 implementation of EmitFPRound 2018-07-16 14:22:29 +01:00
MerryMage
a981d3ffb1 A64: Implement FRINTX, FRINTI (scalar) 2018-07-16 14:10:53 +01:00
MerryMage
aa315c97b9 A64: Implement FRINTP, FRINTM, FRINTZ (scalar) 2018-07-16 14:10:53 +01:00
MerryMage
80aa4f49e6 A64: Implement FRINTN (scalar) 2018-07-16 14:10:53 +01:00
MerryMage
eaf4106620 A64: Implement FRINTA (scalar) 2018-07-16 14:10:53 +01:00
MerryMage
48166d80cd IR: Implement FPRoundInt 2018-07-16 14:10:53 +01:00
MerryMage
f600f48bdd fp: Implement FPRoundInt 2018-07-16 13:50:37 +01:00
MerryMage
a8952a521b fp: Implement FPProcessNaN 2018-07-16 13:50:37 +01:00
MerryMage
4ba4ed2dca fp/info: Add DefaultNaN 2018-07-16 13:50:37 +01:00
MerryMage
b08e49d337 fp: Move FPToFixed to its own file 2018-07-16 13:50:37 +01:00
MerryMage
814092c5be a64_jit_state: Add FPSR.QC flag 2018-07-16 13:50:37 +01:00
Lioncash
54c6d119ba emit_x64_vector: Use non-scratch Use* variants of registers within EmitVectorUnsignedAbsoluteDifference() 
In some cases, a register isn't modified, depending on the branch taken,
so we can signify this by using the non-scratch variants in certain
cases.
 2018-07-16 10:35:51 +01:00
Lioncash
ca579d2603 simd_scalar_two_register_misc: Implement scalar double/single-precision variants of FCM{EQ, GE, GT, LE, LT} (zero) 2018-07-16 10:35:26 +01:00
Lioncash
3b3e1c0991 translate_arm: Remove unnecessary rotr() function 
We already have RotateRight() in our common code, so we can remove this
function and replace it with it. We can also implement ArmExpandImm_C()
in terms of ArmExpandImm().
 2018-07-16 10:32:46 +01:00