935 lines
27 KiB
C++
935 lines
27 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "frontend/A32/translate/impl/translate.h"
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namespace Dynarmic::A32 {
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bool TranslatorVisitor::arm_LDRBT() {
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// System instructions unimplemented
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return UndefinedInstruction();
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}
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bool TranslatorVisitor::arm_LDRHT() {
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// System instructions unimplemented
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return UndefinedInstruction();
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}
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bool TranslatorVisitor::arm_LDRSBT() {
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// System instructions unimplemented
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return UndefinedInstruction();
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}
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bool TranslatorVisitor::arm_LDRSHT() {
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// System instructions unimplemented
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return UndefinedInstruction();
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}
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bool TranslatorVisitor::arm_LDRT() {
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// System instructions unimplemented
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return UndefinedInstruction();
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}
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bool TranslatorVisitor::arm_STRBT() {
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// System instructions unimplemented
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return UndefinedInstruction();
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}
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bool TranslatorVisitor::arm_STRHT() {
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// System instructions unimplemented
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return UndefinedInstruction();
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}
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bool TranslatorVisitor::arm_STRT() {
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// System instructions unimplemented
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return UndefinedInstruction();
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}
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static IR::U32 GetAddress(A32::IREmitter& ir, bool P, bool U, bool W, Reg n, IR::U32 offset) {
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const bool index = P;
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const bool add = U;
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const bool wback = !P || W;
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const IR::U32 offset_addr = add ? ir.Add(ir.GetRegister(n), offset) : ir.Sub(ir.GetRegister(n), offset);
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const IR::U32 address = index ? offset_addr : ir.GetRegister(n);
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if (wback) {
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ir.SetRegister(n, offset_addr);
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}
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return address;
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}
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// LDR <Rt>, [PC, #+/-<imm>]
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bool TranslatorVisitor::arm_LDR_lit(Cond cond, bool U, Reg t, Imm<12> imm12) {
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const bool add = U;
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const u32 base = ir.AlignPC(4);
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const u32 address = add ? (base + imm12.ZeroExtend()) : (base - imm12.ZeroExtend());
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const auto data = ir.ReadMemory32(ir.Imm32(address));
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if (t == Reg::PC) {
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ir.LoadWritePC(data);
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ir.SetTerm(IR::Term::FastDispatchHint{});
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return false;
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}
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ir.SetRegister(t, data);
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return true;
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}
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// LDR <Rt>, [<Rn>, #+/-<imm>]{!}
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// LDR <Rt>, [<Rn>], #+/-<imm>
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bool TranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<12> imm12) {
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if (n == Reg::PC) {
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return UnpredictableInstruction();
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}
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ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
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if ((!P || W) && n == t) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const u32 imm32 = imm12.ZeroExtend();
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const auto offset = ir.Imm32(imm32);
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.ReadMemory32(address);
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if (t == Reg::PC) {
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ir.LoadWritePC(data);
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if (!P && W && n == Reg::R13) {
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ir.SetTerm(IR::Term::PopRSBHint{});
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} else {
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ir.SetTerm(IR::Term::FastDispatchHint{});
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}
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return false;
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}
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ir.SetRegister(t, data);
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return true;
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}
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// LDR <Rt>, [<Rn>, #+/-<Rm>]{!}
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// LDR <Rt>, [<Rn>], #+/-<Rm>
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bool TranslatorVisitor::arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<5> imm5, ShiftType shift, Reg m) {
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ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
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if (m == Reg::PC) {
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return UnpredictableInstruction();
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}
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if ((!P || W) && (n == Reg::PC || n == t)) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const auto offset = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag()).result;
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.ReadMemory32(address);
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if (t == Reg::PC) {
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ir.LoadWritePC(data);
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ir.SetTerm(IR::Term::FastDispatchHint{});
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return false;
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}
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ir.SetRegister(t, data);
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return true;
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}
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// LDRB <Rt>, [PC, #+/-<imm>]
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bool TranslatorVisitor::arm_LDRB_lit(Cond cond, bool U, Reg t, Imm<12> imm12) {
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const u32 imm32 = imm12.ZeroExtend();
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const bool add = U;
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const u32 base = ir.AlignPC(4);
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const u32 address = add ? (base + imm32) : (base - imm32);
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const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(ir.Imm32(address)));
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ir.SetRegister(t, data);
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return true;
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}
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// LDRB <Rt>, [<Rn>, #+/-<imm>]{!}
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// LDRB <Rt>, [<Rn>], #+/-<imm>
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bool TranslatorVisitor::arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<12> imm12) {
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if (n == Reg::PC) {
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return UnpredictableInstruction();
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}
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ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
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if ((!P || W) && n == t) {
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return UnpredictableInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const u32 imm32 = imm12.ZeroExtend();
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const auto offset = ir.Imm32(imm32);
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
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ir.SetRegister(t, data);
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return true;
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}
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// LDRB <Rt>, [<Rn>, #+/-<Rm>]{!}
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// LDRB <Rt>, [<Rn>], #+/-<Rm>
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bool TranslatorVisitor::arm_LDRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<5> imm5, ShiftType shift, Reg m) {
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ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
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if (t == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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if ((!P || W) && (n == Reg::PC || n == t)) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const auto offset = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag()).result;
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.ZeroExtendByteToWord(ir.ReadMemory8(address));
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ir.SetRegister(t, data);
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return true;
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}
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// LDRD <Rt>, <Rt2>, [PC, #+/-<imm>]
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bool TranslatorVisitor::arm_LDRD_lit(Cond cond, bool U, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
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if (RegNumber(t) % 2 == 1) {
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return UnpredictableInstruction();
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}
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if (t+1 == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const Reg t2 = t+1;
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const u32 imm32 = concatenate(imm8a, imm8b).ZeroExtend();
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const bool add = U;
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const u32 base = ir.AlignPC(4);
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const u32 address = add ? (base + imm32) : (base - imm32);
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const auto data_a = ir.ReadMemory32(ir.Imm32(address));
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const auto data_b = ir.ReadMemory32(ir.Imm32(address + 4));
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ir.SetRegister(t, data_a);
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ir.SetRegister(t2, data_b);
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return true;
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}
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// LDRD <Rt>, [<Rn>, #+/-<imm>]{!}
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// LDRD <Rt>, [<Rn>], #+/-<imm>
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bool TranslatorVisitor::arm_LDRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
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if (n == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (RegNumber(t) % 2 == 1) {
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return UnpredictableInstruction();
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}
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if (!P && W) {
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return UnpredictableInstruction();
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}
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if ((!P || W) && (n == t || n == t+1)) {
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return UnpredictableInstruction();
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}
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if (t+1 == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const Reg t2 = t+1;
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const u32 imm32 = concatenate(imm8a, imm8b).ZeroExtend();
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const auto offset = ir.Imm32(imm32);
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const auto address_a = GetAddress(ir, P, U, W, n, offset);
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const auto address_b = ir.Add(address_a, ir.Imm32(4));
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const auto data_a = ir.ReadMemory32(address_a);
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const auto data_b = ir.ReadMemory32(address_b);
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ir.SetRegister(t, data_a);
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ir.SetRegister(t2, data_b);
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return true;
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}
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// LDRD <Rt>, [<Rn>, #+/-<Rm>]{!}
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// LDRD <Rt>, [<Rn>], #+/-<Rm>
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bool TranslatorVisitor::arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
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if (RegNumber(t) % 2 == 1) {
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return UnpredictableInstruction();
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}
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if (!P && W) {
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return UnpredictableInstruction();
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}
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if (t+1 == Reg::PC || m == Reg::PC || m == t || m == t+1) {
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return UnpredictableInstruction();
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}
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if ((!P || W) && (n == Reg::PC || n == t || n == t+1)) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const Reg t2 = t+1;
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const auto offset = ir.GetRegister(m);
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const auto address_a = GetAddress(ir, P, U, W, n, offset);
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const auto address_b = ir.Add(address_a, ir.Imm32(4));
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const auto data_a = ir.ReadMemory32(address_a);
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const auto data_b = ir.ReadMemory32(address_b);
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ir.SetRegister(t, data_a);
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ir.SetRegister(t2, data_b);
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return true;
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}
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// LDRH <Rt>, [PC, #-/+<imm>]
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bool TranslatorVisitor::arm_LDRH_lit(Cond cond, bool P, bool U, bool W, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
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ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
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if (P == W) {
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return UnpredictableInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const u32 imm32 = concatenate(imm8a, imm8b).ZeroExtend();
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const bool add = U;
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const u32 base = ir.AlignPC(4);
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const u32 address = add ? (base + imm32) : (base - imm32);
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const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(ir.Imm32(address)));
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ir.SetRegister(t, data);
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return true;
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}
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// LDRH <Rt>, [<Rn>, #+/-<imm>]{!}
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// LDRH <Rt>, [<Rn>], #+/-<imm>
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bool TranslatorVisitor::arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
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if (n == Reg::PC) {
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return UnpredictableInstruction();
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}
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ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
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if ((!P || W) && n == t) {
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return UnpredictableInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const u32 imm32 = concatenate(imm8a, imm8b).ZeroExtend();
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const auto offset = ir.Imm32(imm32);
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(address));
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ir.SetRegister(t, data);
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return true;
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}
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// LDRH <Rt>, [<Rn>, #+/-<Rm>]{!}
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// LDRH <Rt>, [<Rn>], #+/-<Rm>
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bool TranslatorVisitor::arm_LDRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
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ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
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if (t == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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if ((!P || W) && (n == Reg::PC || n == t)) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const auto offset = ir.GetRegister(m);
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(address));
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ir.SetRegister(t, data);
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return true;
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}
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// LDRSB <Rt>, [PC, #+/-<imm>]
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bool TranslatorVisitor::arm_LDRSB_lit(Cond cond, bool U, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const u32 imm32 = concatenate(imm8a, imm8b).ZeroExtend();
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const bool add = U;
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const u32 base = ir.AlignPC(4);
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const u32 address = add ? (base + imm32) : (base - imm32);
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const auto data = ir.SignExtendByteToWord(ir.ReadMemory8(ir.Imm32(address)));
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ir.SetRegister(t, data);
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return true;
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}
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// LDRSB <Rt>, [<Rn>, #+/-<imm>]{!}
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// LDRSB <Rt>, [<Rn>], #+/-<imm>
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bool TranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
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if (n == Reg::PC) {
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return UnpredictableInstruction();
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}
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ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
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if ((!P || W) && n == t) {
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return UnpredictableInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const u32 imm32 = concatenate(imm8a, imm8b).ZeroExtend();
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const auto offset = ir.Imm32(imm32);
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.SignExtendByteToWord(ir.ReadMemory8(address));
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ir.SetRegister(t, data);
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return true;
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}
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// LDRSB <Rt>, [<Rn>, #+/-<Rm>]{!}
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// LDRSB <Rt>, [<Rn>], #+/-<Rm>
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bool TranslatorVisitor::arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
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ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
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if (t == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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if ((!P || W) && (n == Reg::PC || n == t)) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const auto offset = ir.GetRegister(m);
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const auto address = GetAddress(ir, P, U, W, n, offset);
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const auto data = ir.SignExtendByteToWord(ir.ReadMemory8(address));
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ir.SetRegister(t, data);
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return true;
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}
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// LDRSH <Rt>, [PC, #-/+<imm>]
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bool TranslatorVisitor::arm_LDRSH_lit(Cond cond, bool U, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (!ArmConditionPassed(cond)) {
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return true;
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}
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const u32 imm32 = concatenate(imm8a, imm8b).ZeroExtend();
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const bool add = U;
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const u32 base = ir.AlignPC(4);
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const u32 address = add ? (base + imm32) : (base - imm32);
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const auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(ir.Imm32(address)));
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ir.SetRegister(t, data);
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return true;
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}
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// LDRSH <Rt>, [<Rn>, #+/-<imm>]{!}
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// LDRSH <Rt>, [<Rn>], #+/-<imm>
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bool TranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
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if (n == Reg::PC) {
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return UnpredictableInstruction();
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}
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ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
|
|
if ((!P || W) && n == t) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (t == Reg::PC) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const u32 imm32 = concatenate(imm8a, imm8b).ZeroExtend();
|
|
const auto offset = ir.Imm32(imm32);
|
|
const auto address = GetAddress(ir, P, U, W, n, offset);
|
|
const auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(address));
|
|
|
|
ir.SetRegister(t, data);
|
|
return true;
|
|
}
|
|
|
|
// LDRSH <Rt>, [<Rn>, #+/-<Rm>]{!}
|
|
// LDRSH <Rt>, [<Rn>], #+/-<Rm>
|
|
bool TranslatorVisitor::arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
|
|
ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
|
|
if (t == Reg::PC || m == Reg::PC) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if ((!P || W) && (n == Reg::PC || n == t)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto offset = ir.GetRegister(m);
|
|
const auto address = GetAddress(ir, P, U, W, n, offset);
|
|
const auto data = ir.SignExtendHalfToWord(ir.ReadMemory16(address));
|
|
|
|
ir.SetRegister(t, data);
|
|
return true;
|
|
}
|
|
|
|
// STR <Rt>, [<Rn>, #+/-<imm>]{!}
|
|
// STR <Rt>, [<Rn>], #+/-<imm>
|
|
bool TranslatorVisitor::arm_STR_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<12> imm12) {
|
|
if ((!P || W) && (n == Reg::PC || n == t)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto offset = ir.Imm32(imm12.ZeroExtend());
|
|
const auto address = GetAddress(ir, P, U, W, n, offset);
|
|
ir.WriteMemory32(address, ir.GetRegister(t));
|
|
return true;
|
|
}
|
|
|
|
// STR <Rt>, [<Rn>, #+/-<Rm>]{!}
|
|
// STR <Rt>, [<Rn>], #+/-<Rm>
|
|
bool TranslatorVisitor::arm_STR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<5> imm5, ShiftType shift, Reg m) {
|
|
if (m == Reg::PC) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if ((!P || W) && (n == Reg::PC || n == t)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto offset = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag()).result;
|
|
const auto address = GetAddress(ir, P, U, W, n, offset);
|
|
ir.WriteMemory32(address, ir.GetRegister(t));
|
|
return true;
|
|
}
|
|
|
|
// STRB <Rt>, [<Rn>, #+/-<imm>]{!}
|
|
// STRB <Rt>, [<Rn>], #+/-<imm>
|
|
bool TranslatorVisitor::arm_STRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<12> imm12) {
|
|
if (t == Reg::PC) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if ((!P || W) && (n == Reg::PC || n == t)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto offset = ir.Imm32(imm12.ZeroExtend());
|
|
const auto address = GetAddress(ir, P, U, W, n, offset);
|
|
ir.WriteMemory8(address, ir.LeastSignificantByte(ir.GetRegister(t)));
|
|
return true;
|
|
}
|
|
|
|
// STRB <Rt>, [<Rn>, #+/-<Rm>]{!}
|
|
// STRB <Rt>, [<Rn>], #+/-<Rm>
|
|
bool TranslatorVisitor::arm_STRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<5> imm5, ShiftType shift, Reg m) {
|
|
if (t == Reg::PC || m == Reg::PC) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if ((!P || W) && (n == Reg::PC || n == t)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto offset = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag()).result;
|
|
const auto address = GetAddress(ir, P, U, W, n, offset);
|
|
ir.WriteMemory8(address, ir.LeastSignificantByte(ir.GetRegister(t)));
|
|
return true;
|
|
}
|
|
|
|
// STRD <Rt>, [<Rn>, #+/-<imm>]{!}
|
|
// STRD <Rt>, [<Rn>], #+/-<imm>
|
|
bool TranslatorVisitor::arm_STRD_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
|
|
if (size_t(t) % 2 != 0) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!P && W) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
const Reg t2 = t + 1;
|
|
if ((!P || W) && (n == Reg::PC || n == t || n == t2)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (t2 == Reg::PC) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const u32 imm32 = concatenate(imm8a, imm8b).ZeroExtend();
|
|
const auto offset = ir.Imm32(imm32);
|
|
const auto address_a = GetAddress(ir, P, U, W, n, offset);
|
|
const auto address_b = ir.Add(address_a, ir.Imm32(4));
|
|
const auto value_a = ir.GetRegister(t);
|
|
const auto value_b = ir.GetRegister(t2);
|
|
|
|
ir.WriteMemory32(address_a, value_a);
|
|
ir.WriteMemory32(address_b, value_b);
|
|
return true;
|
|
}
|
|
|
|
// STRD <Rt>, [<Rn>, #+/-<Rm>]{!}
|
|
// STRD <Rt>, [<Rn>], #+/-<Rm>
|
|
bool TranslatorVisitor::arm_STRD_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
|
|
if (size_t(t) % 2 != 0) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!P && W) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
const Reg t2 = t + 1;
|
|
if (t2 == Reg::PC || m == Reg::PC) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if ((!P || W) && (n == Reg::PC || n == t || n == t2)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto offset = ir.GetRegister(m);
|
|
const auto address_a = GetAddress(ir, P, U, W, n, offset);
|
|
const auto address_b = ir.Add(address_a, ir.Imm32(4));
|
|
const auto value_a = ir.GetRegister(t);
|
|
const auto value_b = ir.GetRegister(t2);
|
|
|
|
ir.WriteMemory32(address_a, value_a);
|
|
ir.WriteMemory32(address_b, value_b);
|
|
return true;
|
|
}
|
|
|
|
// STRH <Rt>, [<Rn>, #+/-<imm>]{!}
|
|
// STRH <Rt>, [<Rn>], #+/-<imm>
|
|
bool TranslatorVisitor::arm_STRH_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
|
|
if (t == Reg::PC) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if ((!P || W) && (n == Reg::PC || n == t)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const u32 imm32 = concatenate(imm8a, imm8b).ZeroExtend();
|
|
const auto offset = ir.Imm32(imm32);
|
|
const auto address = GetAddress(ir, P, U, W, n, offset);
|
|
|
|
ir.WriteMemory16(address, ir.LeastSignificantHalf(ir.GetRegister(t)));
|
|
return true;
|
|
}
|
|
|
|
// STRH <Rt>, [<Rn>, #+/-<Rm>]{!}
|
|
// STRH <Rt>, [<Rn>], #+/-<Rm>
|
|
bool TranslatorVisitor::arm_STRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
|
|
if (t == Reg::PC || m == Reg::PC) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if ((!P || W) && (n == Reg::PC || n == t)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto offset = ir.GetRegister(m);
|
|
const auto address = GetAddress(ir, P, U, W, n, offset);
|
|
|
|
ir.WriteMemory16(address, ir.LeastSignificantHalf(ir.GetRegister(t)));
|
|
return true;
|
|
}
|
|
|
|
static bool LDMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 start_address, IR::U32 writeback_address) {
|
|
auto address = start_address;
|
|
for (size_t i = 0; i <= 14; i++) {
|
|
if (Common::Bit(i, list)) {
|
|
ir.SetRegister(static_cast<Reg>(i), ir.ReadMemory32(address));
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
}
|
|
}
|
|
if (W && !Common::Bit(RegNumber(n), list)) {
|
|
ir.SetRegister(n, writeback_address);
|
|
}
|
|
if (Common::Bit<15>(list)) {
|
|
ir.LoadWritePC(ir.ReadMemory32(address));
|
|
if (n == Reg::R13)
|
|
ir.SetTerm(IR::Term::PopRSBHint{});
|
|
else
|
|
ir.SetTerm(IR::Term::FastDispatchHint{});
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
// LDM <Rn>{!}, <reg_list>
|
|
bool TranslatorVisitor::arm_LDM(Cond cond, bool W, Reg n, RegList list) {
|
|
if (n == Reg::PC || Common::BitCount(list) < 1) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
if (W && Common::Bit(static_cast<size_t>(n), list)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto start_address = ir.GetRegister(n);
|
|
const auto writeback_address = ir.Add(start_address, ir.Imm32(u32(Common::BitCount(list) * 4)));
|
|
return LDMHelper(ir, W, n, list, start_address, writeback_address);
|
|
}
|
|
|
|
// LDMDA <Rn>{!}, <reg_list>
|
|
bool TranslatorVisitor::arm_LDMDA(Cond cond, bool W, Reg n, RegList list) {
|
|
if (n == Reg::PC || Common::BitCount(list) < 1) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
if (W && Common::Bit(static_cast<size_t>(n), list)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(u32(4 * Common::BitCount(list) - 4)));
|
|
const auto writeback_address = ir.Sub(start_address, ir.Imm32(4));
|
|
return LDMHelper(ir, W, n, list, start_address, writeback_address);
|
|
}
|
|
|
|
// LDMDB <Rn>{!}, <reg_list>
|
|
bool TranslatorVisitor::arm_LDMDB(Cond cond, bool W, Reg n, RegList list) {
|
|
if (n == Reg::PC || Common::BitCount(list) < 1) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
if (W && Common::Bit(static_cast<size_t>(n), list)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(u32(4 * Common::BitCount(list))));
|
|
const auto writeback_address = start_address;
|
|
return LDMHelper(ir, W, n, list, start_address, writeback_address);
|
|
}
|
|
|
|
// LDMIB <Rn>{!}, <reg_list>
|
|
bool TranslatorVisitor::arm_LDMIB(Cond cond, bool W, Reg n, RegList list) {
|
|
if (n == Reg::PC || Common::BitCount(list) < 1) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
if (W && Common::Bit(static_cast<size_t>(n), list)) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto start_address = ir.Add(ir.GetRegister(n), ir.Imm32(4));
|
|
const auto writeback_address = ir.Add(ir.GetRegister(n), ir.Imm32(u32(4 * Common::BitCount(list))));
|
|
return LDMHelper(ir, W, n, list, start_address, writeback_address);
|
|
}
|
|
|
|
bool TranslatorVisitor::arm_LDM_usr() {
|
|
return InterpretThisInstruction();
|
|
}
|
|
|
|
bool TranslatorVisitor::arm_LDM_eret() {
|
|
return InterpretThisInstruction();
|
|
}
|
|
|
|
static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 start_address, IR::U32 writeback_address) {
|
|
auto address = start_address;
|
|
for (size_t i = 0; i <= 14; i++) {
|
|
if (Common::Bit(i, list)) {
|
|
ir.WriteMemory32(address, ir.GetRegister(static_cast<Reg>(i)));
|
|
address = ir.Add(address, ir.Imm32(4));
|
|
}
|
|
}
|
|
if (W) {
|
|
ir.SetRegister(n, writeback_address);
|
|
}
|
|
if (Common::Bit<15>(list)) {
|
|
ir.WriteMemory32(address, ir.Imm32(ir.PC()));
|
|
}
|
|
return true;
|
|
}
|
|
|
|
// STM <Rn>{!}, <reg_list>
|
|
bool TranslatorVisitor::arm_STM(Cond cond, bool W, Reg n, RegList list) {
|
|
if (n == Reg::PC || Common::BitCount(list) < 1) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto start_address = ir.GetRegister(n);
|
|
const auto writeback_address = ir.Add(start_address, ir.Imm32(u32(Common::BitCount(list) * 4)));
|
|
return STMHelper(ir, W, n, list, start_address, writeback_address);
|
|
}
|
|
|
|
// STMDA <Rn>{!}, <reg_list>
|
|
bool TranslatorVisitor::arm_STMDA(Cond cond, bool W, Reg n, RegList list) {
|
|
if (n == Reg::PC || Common::BitCount(list) < 1) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(u32(4 * Common::BitCount(list) - 4)));
|
|
const auto writeback_address = ir.Sub(start_address, ir.Imm32(4));
|
|
return STMHelper(ir, W, n, list, start_address, writeback_address);
|
|
}
|
|
|
|
// STMDB <Rn>{!}, <reg_list>
|
|
bool TranslatorVisitor::arm_STMDB(Cond cond, bool W, Reg n, RegList list) {
|
|
if (n == Reg::PC || Common::BitCount(list) < 1) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(u32(4 * Common::BitCount(list))));
|
|
const auto writeback_address = start_address;
|
|
return STMHelper(ir, W, n, list, start_address, writeback_address);
|
|
}
|
|
|
|
// STMIB <Rn>{!}, <reg_list>
|
|
bool TranslatorVisitor::arm_STMIB(Cond cond, bool W, Reg n, RegList list) {
|
|
if (n == Reg::PC || Common::BitCount(list) < 1) {
|
|
return UnpredictableInstruction();
|
|
}
|
|
|
|
if (!ArmConditionPassed(cond)) {
|
|
return true;
|
|
}
|
|
|
|
const auto start_address = ir.Add(ir.GetRegister(n), ir.Imm32(4));
|
|
const auto writeback_address = ir.Add(ir.GetRegister(n), ir.Imm32(u32(4 * Common::BitCount(list))));
|
|
return STMHelper(ir, W, n, list, start_address, writeback_address);
|
|
}
|
|
|
|
bool TranslatorVisitor::arm_STM_usr() {
|
|
return InterpretThisInstruction();
|
|
}
|
|
|
|
} // namespace Dynarmic::A32
|