101 lines
2.6 KiB
ArmAsm
101 lines
2.6 KiB
ArmAsm
.section ".init"
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.global _start
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.extern main
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.align 4
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.arm
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#define SIZE_32KB 0b01110
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#define SIZE_128KB 0b10000
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#define SIZE_512KB 0b10010
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#define SIZE_2MB 0b10100
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#define SIZE_128MB 0b11010
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#define SIZE_256MB 0b11011
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#define SIZE_4GB 0b11111
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@ Makes a MPU partition value
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#define MAKE_PARTITION(offset, size_enum) \
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(((offset) >> 12 << 12) | ((size_enum) << 1) | 1)
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_start:
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b _init
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@ required, don't move :)
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@ will be set to FIRM ARM9 entry point by BRAHMA
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arm9ep_backup: .long 0xFFFF0000
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_mpu_partition_table:
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.word MAKE_PARTITION(0x00000000, SIZE_4GB) @ 0: Background region
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.word MAKE_PARTITION(0x00000000, SIZE_128MB) @ 1: Instruction TCM (mirrored every 32KB)
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.word MAKE_PARTITION(0x08000000, SIZE_2MB) @ 2: ARM9 internal memory
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.word MAKE_PARTITION(0x10000000, SIZE_128MB) @ 3: IO region
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.word MAKE_PARTITION(0x18000000, SIZE_128MB) @ 4: external device memory
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.word MAKE_PARTITION(0x1FF80000, SIZE_512KB) @ 5: AXI WRAM
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.word MAKE_PARTITION(0x20000000, SIZE_256MB) @ 6: FCRAM
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.word 0 @ 7: Unused
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_populate_mpu:
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push {r4-r5, lr}
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ldr r4, =_mpu_partition_table
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ldr r5, [r4, #0x0] @ mmu_partition_table[0] load
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mcr p15, 0, r5, c6, c0, 0 @ mmu_partition_table[0] write
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ldr r5, [r4, #0x4]
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mcr p15, 0, r5, c6, c1, 0
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ldr r5, [r4, #0x8]
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mcr p15, 0, r5, c6, c2, 0
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ldr r5, [r4, #0xC]
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mcr p15, 0, r5, c6, c3, 0
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ldr r5, [r4, #0x10]
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mcr p15, 0, r5, c6, c4, 0
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ldr r5, [r4, #0x14]
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mcr p15, 0, r5, c6, c5, 0
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ldr r5, [r4, #0x18]
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mcr p15, 0, r5, c6, c6, 0
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@ Give read/write access to all the memory regions
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ldr r5, =0x03333333
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mcr p15, 0, r5, c5, c0, 2 @ data access
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ldr r5, =0x03300330
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mcr p15, 0, r5, c5, c0, 3 @ instruction access
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mov r5, #0x72
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mcr p15, 0, r5, c2, c0, 0 @ data cachable
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mcr p15, 0, r5, c2, c0, 1 @ instruction cachable
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mov r5, #0x10
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mcr p15, 0, r5, c3, c0, 0 @ data bufferable
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pop {r4-r5, pc}
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_enable_caches:
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push {r4-r5, lr}
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bl _populate_mpu
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mov r5, #0
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mcr p15, 0, r5, c7, c5, 0 @ flush I-cache
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mcr p15, 0, r5, c7, c6, 0 @ flush D-cache
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mrc p15, 0, r4, c1, c0, 0
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orr r4, r4, #(1<<12) @ instruction cache enable
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orr r4, r4, #(1<<2) @ data cache enable
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orr r4, r4, #(1<<0) @ mpu enable
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mcr p15, 0, r4, c1, c0, 0
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pop {r4-r5, pc}
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_init:
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push {r0-r12, lr}
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bl _enable_caches
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bl main
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mrc p15, 0, r4, c1, c0, 0
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bic r4, r4, #(1<<0) @ mpu disable
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mcr p15, 0, r4, c1, c0, 0
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pop {r0-r12, lr}
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@ return control to FIRM
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ldr pc, arm9ep_backup
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