From c0fe74a321ba97e999537baf32e468f34a42cd7c Mon Sep 17 00:00:00 2001 From: Amos <k.mazidjatari@gmail.com> Date: Sat, 11 Feb 2023 16:31:53 +0100 Subject: [PATCH] Set cache desc to whole descriptor for Intel CPU's --- r5dev/tier0/cpu.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/r5dev/tier0/cpu.cpp b/r5dev/tier0/cpu.cpp index 021588b2..681d0ce0 100644 --- a/r5dev/tier0/cpu.cpp +++ b/r5dev/tier0/cpu.cpp @@ -521,7 +521,7 @@ const CPUInformation& GetCPUInformation(void) uint32_t nCacheSizeBytes = nCacheWays * nCachePartitions * nCacheLineSize * nCacheSets; nCacheSizeKiB[nCacheLevel] = nCacheSizeBytes >> 10; - nCacheDesc[nCacheLevel] = ((nCacheWays << 16) + (nCachePartitions << 8) + nCacheLineSize); + nCacheDesc[nCacheLevel] = 1 + cpuid4.ebx; } } } @@ -574,7 +574,10 @@ const CPUInformation& GetCPUInformation(void) if (cpuid0ex.eax >= 0x80000006) { // Make sure we got the L2 cache info right. - pi.m_nL2CacheSizeKb = (cpuid(0x80000006).ecx >> 16); + CpuIdResult_t cpuid6ex = cpuid(0x80000006); + + pi.m_nL2CacheSizeKb = cpuid6ex.ecx >> 16; + pi.m_nL2CacheDesc = cpuid6ex.ecx & 0xFFFF; } } return pi;