mirror of
https://github.com/Mauler125/r5sdk.git
synced 2025-02-09 19:15:03 +01:00
Make SSE mask constants unsigned
Should be unsigned to avoid compile errors (clang-cl); this did not affect code generation.
This commit is contained in:
Kawe Mazidjatari
parent
69624baa10
commit
d2a8d077a6
@ -5,12 +5,12 @@
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//===========================================================================//
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#if defined(__SPU__)
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#include "platform.h"
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#include "basetypes.h"
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#include "tier0/platform.h"
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#include "tier0/basetypes.h"
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#include "mathlib/mathlib.h"
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#include "mathlib/math_pfns.h"
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// #include "mathlib/fltx4.h"
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#include "ps3/spu_job_shared.h"
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//#include "ps3/spu_job_shared.h"
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#endif
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#include "core/stdafx.h"
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@ -21,6 +21,11 @@
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// NOTE: This has to be the last file included!
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//#include "tier0/memdbgon.h"
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const fltx4 g_SIMD_Identity[4] =
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{
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{ 1.0, 0, 0, 0 }, { 0, 1.0, 0, 0 }, { 0, 0, 1.0, 0 }, { 0, 0, 0, 1.0 }
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};
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#if !defined(__SPU__)
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const fltx4 Four_PointFives = { 0.5,0.5,0.5,0.5 };
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#ifndef _X360
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@ -68,25 +73,20 @@ const fltx4 g_QuatMultRowSign[4] =
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#endif
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const int32 ALIGN16 g_SIMD_clear_signmask[4] ALIGN16_POST = { 0x7fffffff,0x7fffffff,0x7fffffff,0x7fffffff };
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const int32 ALIGN16 g_SIMD_signmask[4] ALIGN16_POST = { 0x80000000, 0x80000000, 0x80000000, 0x80000000 };
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const int32 ALIGN16 g_SIMD_lsbmask[4] ALIGN16_POST = { 0xfffffffe, 0xfffffffe, 0xfffffffe, 0xfffffffe };
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const int32 ALIGN16 g_SIMD_clear_wmask[4] ALIGN16_POST = { 0xffffffff, 0xffffffff, 0xffffffff, 0 };
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const int32 ALIGN16 g_SIMD_AllOnesMask[4] ALIGN16_POST = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; // ~0,~0,~0,~0
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const int32 ALIGN16 g_SIMD_Low16BitsMask[4] ALIGN16_POST = { 0xffff, 0xffff, 0xffff, 0xffff }; // 0xffff x 4
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const uint32 ALIGN16 g_SIMD_clear_signmask[4] ALIGN16_POST = { 0x7fffffff,0x7fffffff,0x7fffffff,0x7fffffff };
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const uint32 ALIGN16 g_SIMD_signmask[4] ALIGN16_POST = { 0x80000000, 0x80000000, 0x80000000, 0x80000000 };
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const uint32 ALIGN16 g_SIMD_lsbmask[4] ALIGN16_POST = { 0xfffffffe, 0xfffffffe, 0xfffffffe, 0xfffffffe };
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const uint32 ALIGN16 g_SIMD_clear_wmask[4] ALIGN16_POST = { 0xffffffff, 0xffffffff, 0xffffffff, 0 };
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const uint32 ALIGN16 g_SIMD_AllOnesMask[4] ALIGN16_POST = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; // ~0,~0,~0,~0
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const uint32 ALIGN16 g_SIMD_Low16BitsMask[4] ALIGN16_POST = { 0xffff, 0xffff, 0xffff, 0xffff }; // 0xffff x 4
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const int32 ALIGN16 g_SIMD_ComponentMask[4][4] ALIGN16_POST =
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const uint32 ALIGN16 g_SIMD_ComponentMask[4][4] ALIGN16_POST =
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{
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{ 0xFFFFFFFF, 0, 0, 0 }, { 0, 0xFFFFFFFF, 0, 0 }, { 0, 0, 0xFFFFFFFF, 0 }, { 0, 0, 0, 0xFFFFFFFF }
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};
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const fltx4 g_SIMD_Identity[4] =
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{
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{ 1.0, 0, 0, 0 }, { 0, 1.0, 0, 0 }, { 0, 0, 1.0, 0 }, { 0, 0, 0, 1.0 }
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};
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const int32 ALIGN16 g_SIMD_SkipTailMask[4][4] ALIGN16_POST =
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const uint32 ALIGN16 g_SIMD_SkipTailMask[4][4] ALIGN16_POST =
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{
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{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff },
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{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000 },
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@ -94,7 +94,7 @@ const int32 ALIGN16 g_SIMD_SkipTailMask[4][4] ALIGN16_POST =
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{ 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000 },
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};
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const int32 ALIGN16 g_SIMD_EveryOtherMask[4] = { 0, ~0, 0, ~0 };
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const uint32 ALIGN16 g_SIMD_EveryOtherMask[4] = { 0, 0xffffffff, 0, 0xffffffff }; // 0,~0,0,~0
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@ -170,20 +170,21 @@ extern const fltx4 Four_GammaToLinearCoefficients_D; // *x^0
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#ifndef ALIGN16_POST
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#define ALIGN16_POST
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#endif
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extern const ALIGN16 int32 g_SIMD_clear_signmask[] ALIGN16_POST; // 0x7fffffff x 4
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extern const ALIGN16 int32 g_SIMD_signmask[] ALIGN16_POST; // 0x80000000 x 4
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extern const ALIGN16 int32 g_SIMD_lsbmask[] ALIGN16_POST; // 0xfffffffe x 4
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extern const ALIGN16 int32 g_SIMD_clear_wmask[] ALIGN16_POST; // -1 -1 -1 0
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extern const ALIGN16 int32 g_SIMD_ComponentMask[4][4] ALIGN16_POST; // [0xFFFFFFFF 0 0 0], [0 0xFFFFFFFF 0 0], [0 0 0xFFFFFFFF 0], [0 0 0 0xFFFFFFFF]
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extern const ALIGN16 int32 g_SIMD_AllOnesMask[] ALIGN16_POST; // ~0,~0,~0,~0
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extern const fltx4 g_SIMD_Identity[4]; // [1 0 0 0], [0 1 0 0], [0 0 1 0], [0 0 0 1]
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extern const ALIGN16 int32 g_SIMD_Low16BitsMask[] ALIGN16_POST; // 0xffff x 4
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extern const ALIGN16 uint32 g_SIMD_clear_signmask[] ALIGN16_POST; // 0x7fffffff x 4
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extern const ALIGN16 uint32 g_SIMD_signmask[] ALIGN16_POST; // 0x80000000 x 4
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extern const ALIGN16 uint32 g_SIMD_lsbmask[] ALIGN16_POST; // 0xfffffffe x 4
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extern const ALIGN16 uint32 g_SIMD_clear_wmask[] ALIGN16_POST; // -1 -1 -1 0
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extern const ALIGN16 uint32 g_SIMD_ComponentMask[4][4] ALIGN16_POST; // [0xFFFFFFFF 0 0 0], [0 0xFFFFFFFF 0 0], [0 0 0xFFFFFFFF 0], [0 0 0 0xFFFFFFFF]
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extern const ALIGN16 uint32 g_SIMD_AllOnesMask[] ALIGN16_POST; // ~0,~0,~0,~0
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extern const ALIGN16 uint32 g_SIMD_Low16BitsMask[] ALIGN16_POST; // 0xffff x 4
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// this mask is used for skipping the tail of things. If you have N elements in an array, and wish
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// to mask out the tail, g_SIMD_SkipTailMask[N & 3] what you want to use for the last iteration.
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extern const int32 ALIGN16 g_SIMD_SkipTailMask[4][4] ALIGN16_POST;
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extern const uint32 ALIGN16 g_SIMD_SkipTailMask[4][4] ALIGN16_POST;
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extern const int32 ALIGN16 g_SIMD_EveryOtherMask[]; // 0, ~0, 0, ~0
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extern const uint32 ALIGN16 g_SIMD_EveryOtherMask[]; // 0, ~0, 0, ~0
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// Define prefetch macros.
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// The characteristics of cache and prefetch are completely
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// different between the different platforms, so you DO NOT
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@ -3653,7 +3654,7 @@ FORCEINLINE fltx4 ReplicateX4(const float* flValue)
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FORCEINLINE float SubFloat(const fltx4& a, int idx)
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{
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// NOTE: if the output goes into a register, this causes a Load-Hit-Store stall (don't mix fpu/vpu math!)
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#ifndef POSIX
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#ifndef POSIX_MATH
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return a.m128_f32[idx];
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#else
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return (reinterpret_cast<float const*>(&a))[idx];
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@ -3662,7 +3663,7 @@ FORCEINLINE float SubFloat(const fltx4& a, int idx)
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FORCEINLINE float& SubFloat(fltx4& a, int idx)
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{
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#ifndef POSIX
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#ifndef POSIX_MATH
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return a.m128_f32[idx];
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#else
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return (reinterpret_cast<float*>(&a))[idx];
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@ -3676,7 +3677,7 @@ FORCEINLINE uint32 SubFloatConvertToInt(const fltx4& a, int idx)
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FORCEINLINE uint32 SubInt(const fltx4& a, int idx)
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{
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#ifndef POSIX
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#ifndef POSIX_MATH
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return a.m128_u32[idx];
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#else
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return (reinterpret_cast<uint32 const*>(&a))[idx];
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@ -3685,7 +3686,7 @@ FORCEINLINE uint32 SubInt(const fltx4& a, int idx)
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FORCEINLINE uint32& SubInt(fltx4& a, int idx)
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{
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#ifndef POSIX
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#ifndef POSIX_MATH
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return a.m128_u32[idx];
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#else
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return (reinterpret_cast<uint32*>(&a))[idx];
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@ -4248,7 +4249,7 @@ FORCEINLINE fltx4 CompressSIMD(fltx4 const& a, fltx4 const& b)
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// using it heavily.
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FORCEINLINE fltx4 LoadAndConvertUint16SIMD(const uint16* pInts)
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{
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#ifdef POSIX
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#ifdef POSIX_MATH
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fltx4 retval;
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SubFloat(retval, 0) = pInts[0];
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SubFloat(retval, 1) = pInts[1];
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@ -4398,7 +4399,7 @@ FORCEINLINE void RotateLeftDoubleSIMD(fltx4& a, fltx4& b)
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// // Some convenience operator overloads, which are just aliasing the functions above.
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// Unneccessary on 360, as you already have them from xboxmath.h (same for PS3 PPU and SPU)
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#if !defined(PLATFORM_PPC) && !defined( POSIX ) && !defined(SPU)
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#if !defined(PLATFORM_PPC) && !defined( POSIX_MATH ) && !defined(SPU)
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#if 1 // TODO: verify generation of non-bad code.
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// Componentwise add
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FORCEINLINE fltx4 operator+(FLTX4 a, FLTX4 b)
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@ -5240,19 +5241,13 @@ inline FourVectors minimum(const FourVectors& a, const FourVectors& b)
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FORCEINLINE FourVectors RotateLeft(const FourVectors& src)
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{
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FourVectors ret;
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ret.x = RotateLeft(src.x);
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ret.y = RotateLeft(src.y);
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ret.z = RotateLeft(src.z);
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FourVectors ret = RotateLeft(src);
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return ret;
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}
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FORCEINLINE FourVectors RotateRight(const FourVectors& src)
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{
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FourVectors ret;
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ret.x = RotateRight(src.x);
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ret.y = RotateRight(src.y);
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ret.z = RotateRight(src.z);
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FourVectors ret = RotateRight(src);
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return ret;
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}
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FORCEINLINE FourVectors MaskedAssign(const bi32x4& ReplacementMask, const FourVectors& NewValue, const FourVectors& OldValue)
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