mirror of
https://github.com/Mauler125/r5sdk.git
synced 2025-02-09 19:15:03 +01:00
723052eb6f
Structure now fully aligns with that of the engine, with exception of newly added fields for the SDK (new fields are marked in the structure definition).
575 lines
16 KiB
C++
575 lines
16 KiB
C++
//===== Copyright (c) 1996-2005, Valve Corporation, All rights reserved. ======//
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//
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// Purpose:
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//
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// $NoKeywords: $
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//=============================================================================//
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#include "tier0/cpu.h"
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#include "tier0/cputopology.h"
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#include "tier0/fasttimer.h"
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/*******************************************************************************/
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static CPUInformation s_cpuInformation;
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static char s_CpuVendorID[13] = "unknown";
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bool s_bCpuBrandInitialized = false;
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bool s_bCpuVendorIdInitialized = false;
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static CpuBrand_t s_CpuBrand;
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/*******************************************************************************/
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struct IntelCacheDesc_t
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{
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uint8_t nDesc;
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uint16_t nCacheSize;
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};
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/*******************************************************************************/
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inline static IntelCacheDesc_t s_IntelL1DataCacheDesc[] = {
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{ 0xA, 8 },
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{ 0xC, 16 },
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{ 0xD, 16 },
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{ 0x2C, 32 },
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{ 0x30, 32 },
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{ 0x60, 16 },
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{ 0x66, 8 },
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{ 0x67, 16 },
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{ 0x68, 32 }
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};
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inline static IntelCacheDesc_t s_IntelL2DataCacheDesc[] =
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{
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{ 0x21, 256 },
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{ 0x39, 128 },
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{ 0x3a, 192 },
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{ 0x3b, 128 },
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{ 0x3c, 256 },
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{ 0x3D, 384 },
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{ 0x3E, 512 },
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{ 0x41, 128 },
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{ 0x42, 256 },
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{ 0x43, 512 },
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{ 0x44, 1024 },
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{ 0x45, 2048 },
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{ 0x48, 3 * 1024 },
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{ 0x4e, 6 * 1024 },
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{ 0x78, 1024 },
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{ 0x79, 128 },
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{ 0x7a, 256 },
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{ 0x7b, 512 },
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{ 0x7c, 1024 },
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{ 0x7d, 2048 },
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{ 0x7f, 512 },
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{ 0x82, 256 },
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{ 0x83, 512 },
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{ 0x84, 1024 },
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{ 0x85, 2048 },
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{ 0x86, 512 },
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{ 0x87, 1024 }
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};
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inline static IntelCacheDesc_t s_IntelL3DataCacheDesc[] = {
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{ 0x22, 512 },
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{ 0x23, 1024 },
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{ 0x25, 2 * 1024 },
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{ 0x29, 4 * 1024 },
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{ 0x46, 4 * 1024 },
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{ 0x47, 8 * 1024 },
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{ 0x49, 4 * 1024 }, // Only valid when: family == 0x0F && model == 0x06.
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{ 0x4a, 6 * 1024 },
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{ 0x4b, 8 * 1024 },
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{ 0x4c, 12 * 1024 },
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{ 0x4d, 16 * 1014 },
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{ 0xD0, 512 },
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{ 0xD1, 1024 },
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{ 0xD2, 2048 },
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{ 0xD6, 1024 },
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{ 0xD7, 2048 },
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{ 0xD8, 4096 },
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{ 0xDC, 1536 },
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{ 0xDD, 3 * 1024 },
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{ 0xDE, 6 * 1024 },
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{ 0xE2, 2048 },
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{ 0xE3, 4096 },
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{ 0xE4, 8 * 1024 },
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{ 0xEA, 12 * 1024 },
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{ 0xEB, 18 * 1024 },
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{ 0xEC, 24 * 1024 }
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};
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/*******************************************************************************/
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static bool cpuid(unsigned long function, CpuIdResult_t& out)
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{
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int pCPUInfo[4];
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__cpuid(pCPUInfo, static_cast<int>(function));
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out.eax = pCPUInfo[0];
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out.ebx = pCPUInfo[1];
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out.ecx = pCPUInfo[2];
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out.edx = pCPUInfo[3];
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return true;
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}
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static bool cpuidex(unsigned long function, unsigned long subfunction, CpuIdResult_t& out)
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{
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int pCPUInfo[4];
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__cpuidex(pCPUInfo, static_cast<int>(function), static_cast<int>(subfunction));
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out.eax = pCPUInfo[0];
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out.ebx = pCPUInfo[1];
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out.ecx = pCPUInfo[2];
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out.edx = pCPUInfo[3];
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return true;
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}
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static CpuIdResult_t cpuid(unsigned long function)
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{
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CpuIdResult_t out;
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if (!cpuid(function, out))
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{
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out.Reset();
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}
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return out;
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}
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static CpuIdResult_t cpuidex(unsigned long function, unsigned long subfunction)
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{
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CpuIdResult_t out;
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if (!cpuidex(function, subfunction, out))
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{
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out.Reset();
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}
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return out;
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}
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/*******************************************************************************/
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bool CheckSSETechnology(void)
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{
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return (cpuid(1).edx & 0x2000000L) != 0;
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}
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bool CheckSSE2Technology(void)
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{
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return (cpuid(1).edx & 0x04000000) != 0;
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}
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bool CheckSSE3Technology(void)
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{
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return (cpuid(1).ecx & 0x00000001) != 0; // bit 1 of ECX.
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}
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bool CheckSSSE3Technology(void)
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{
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// SSSE 3 is implemented by both Intel and AMD.
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// Detection is done the same way for both vendors.
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return (cpuid(1).ecx & (1 << 9)) != 0; // bit 9 of ECX.
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}
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bool CheckSSE41Technology(void)
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{
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// SSE 4.1 is implemented by both Intel and AMD.
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// Detection is done the same way for both vendors.
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return (cpuid(1).ecx & (1 << 19)) != 0; // bit 19 of ECX.
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}
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bool CheckSSE42Technology(void)
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{
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// SSE4.2 is an Intel-only feature.
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const char* pchVendor = GetProcessorVendorId();
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if (0 != _stricmp(pchVendor, "GenuineIntel"))
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{
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return false;
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}
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return (cpuid(1).ecx & (1 << 20)) != 0; // bit 20 of ECX.
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}
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bool CheckSSE4aTechnology(void)
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{
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// SSE 4a is an AMD-only feature.
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const char* pchVendor = GetProcessorVendorId();
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if (0 != _stricmp(pchVendor, "AuthenticAMD"))
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{
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return false;
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}
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return (cpuid(1).ecx & (1 << 6)) != 0; // bit 6 of ECX.
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}
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bool Check3DNowTechnology(void)
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{
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if (cpuid(0x80000000).eax > 0x80000000L)
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{
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return (cpuid(0x80000001).eax & (1 << 31)) != 0;
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}
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return false;
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}
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bool CheckCMOVTechnology(void)
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{
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return (cpuid(1).edx & (1 << 15)) != 0;
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}
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bool CheckFCMOVTechnology(void)
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{
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return (cpuid(1).edx & (1 << 16)) != 0;
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}
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bool CheckRDTSCTechnology(void)
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{
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return (cpuid(1).edx & 0x10) != 0;
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}
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// Return the Processor's vendor identification string, or "Generic_x86" if it doesn't exist on this CPU.
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const char* GetProcessorVendorId(void)
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{
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if (s_bCpuVendorIdInitialized)
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{
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return s_CpuVendorID;
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}
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s_bCpuVendorIdInitialized = true;
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CpuIdResult_t cpuid0 = cpuid(0);
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memset(s_CpuVendorID, 0, sizeof(s_CpuVendorID));
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if (!cpuid0.eax)
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{
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strcpy(s_CpuVendorID, ("Generic_x86"));
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}
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else
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{
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memcpy(s_CpuVendorID + 0, &(cpuid0.ebx), sizeof(cpuid0.ebx));
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memcpy(s_CpuVendorID + 4, &(cpuid0.edx), sizeof(cpuid0.edx));
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memcpy(s_CpuVendorID + 8, &(cpuid0.ecx), sizeof(cpuid0.ecx));
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}
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return s_CpuVendorID;
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}
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const char* GetProcessorBrand(bool bRemovePadding = true)
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{
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if (s_bCpuBrandInitialized)
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{
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return s_CpuBrand.name;
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}
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s_bCpuBrandInitialized = true;
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memset(&s_CpuBrand, '\0', sizeof(s_CpuBrand));
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const char* pchVendor = GetProcessorVendorId();
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if (0 == _stricmp(pchVendor, "AuthenticAMD") || 0 == _stricmp(pchVendor, "GenuineIntel"))
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{
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// AMD/Intel brand string.
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if (cpuid(0x80000000).eax >= 0x80000004)
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{
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s_CpuBrand.cpuid[0] = cpuid(0x80000002);
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s_CpuBrand.cpuid[1] = cpuid(0x80000003);
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s_CpuBrand.cpuid[2] = cpuid(0x80000004);
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}
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}
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if (bRemovePadding)
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{
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for (size_t i = sizeof(s_CpuBrand.name); i-- > 0; )
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{
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if (s_CpuBrand.name[i] != '\0')
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{
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if (s_CpuBrand.name[i] != ' ')
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{
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if (i < (sizeof(s_CpuBrand.name) - 1))
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{
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s_CpuBrand.name[i + 1] = '\0';
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break;
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}
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}
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}
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}
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}
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return s_CpuBrand.name;
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}
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/*******************************************************************************/
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// Returns non-zero if Hyper-Threading Technology is supported on the processors and zero if not.
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// If it's supported, it does not mean that it's been enabled. So we test another flag to see if it's enabled
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// See Intel Processor Identification and the CPUID instruction Application Note 485.
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// http://www.intel.com/Assets/PDF/appnote/241618.pdf
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static bool HTSupported(void)
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{
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enum {
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HT_BIT = 0x10000000,// EDX[28] - Bit 28 set indicates Hyper-Threading Technology is supported in hardware.
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FAMILY_ID = 0x0f00, // EAX[11:8] - Bit 11 thru 8 contains family processor id.
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EXT_FAMILY_ID = 0x0f00000, // EAX[23:20] - Bit 23 thru 20 contains extended family processor id.
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FAMILY_ID_386 = 0x0300,
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FAMILY_ID_486 = 0x0400, // EAX[8:12] - 486, 487 and overdrive.
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FAMILY_ID_PENTIUM = 0x0500, // Pentium, Pentium OverDrive 60 - 200.
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FAMILY_ID_PENTIUM_PRO = 0x0600, // P Pro, P II, P III, P M, Celeron M, Core Duo, Core Solo, Core2 Duo, Core2 Extreme, P D, Xeon model F,
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// also 45-nm : Intel Atom, Core i7, Xeon MP ; see Intel Processor Identification and the CPUID instruction pg 20,21.
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FAMILY_ID_EXTENDED = 0x0F00 // P IV, Xeon, Celeron D, P D, .
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};
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// This works on both newer AMD and Intel CPUs.
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CpuIdResult_t cpuid1 = cpuid(1);
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// Previously, we detected P4 specifically; now, we detect GenuineIntel with HT enabled in general.
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// if (((cpuid1.eax & FAMILY_ID) == FAMILY_ID_EXTENDED) || (cpuid1.eax & EXT_FAMILY_ID))
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// Check to see if this is an Intel Processor with HT or CMT capability , and if HT/CMT is enabled.
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// ddk: This codef is actually correct: see example code at http://software.intel.com/en-us/articles/multi-core-detect/
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return (cpuid1.edx & HT_BIT) != 0 && // Genuine Intel Processor with Hyper-Threading Technology implemented.
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((cpuid1.ebx >> 16) & 0xFF) > 1; // Hyper-Threading OR Core Multi-Processing has been enabled.
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}
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// | Commented out as its currently unused, this is to avoid a compiler warning |
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// | regarding unused function of static linkage. |
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// Returns the number of logical processors per physical processors.
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//static uint8_t LogicalProcessorsPerPackage(void)
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//{
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// // EBX[23:16] indicate number of logical processors per package.
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// const unsigned NUM_LOGICAL_BITS = 0x00FF0000;
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//
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// if (!HTSupported())
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// {
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// return 1;
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// }
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//
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// return static_cast<uint8_t>(((cpuid(1).ebx & NUM_LOGICAL_BITS) >> 16));
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//}
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// Measure the processor clock speed by sampling the cycle count, waiting
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// for some fraction of a second, then measuring the elapsed number of cycles.
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static int64 CalculateClockSpeed(void)
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{
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LARGE_INTEGER waitTime, startCount, curCount;
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CCycleCount start, end;
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// Take 1/32 of a second for the measurement.
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QueryPerformanceFrequency(&waitTime);
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int scale = 5;
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waitTime.QuadPart >>= scale;
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QueryPerformanceCounter(&startCount);
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start.Sample();
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do
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{
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QueryPerformanceCounter(&curCount);
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} while (curCount.QuadPart - startCount.QuadPart < waitTime.QuadPart);
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end.Sample();
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return (end.GetLongCycles() - start.GetLongCycles()) << scale;
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}
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static void FindIntelCacheDesc(uint8_t nDesc, const IntelCacheDesc_t* pDesc, int nDescCount, uint32_t& nCache, uint32_t& nCacheDesc)
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{
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for (int i = 0; i < nDescCount; ++i)
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{
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const IntelCacheDesc_t& desc = pDesc[i];
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if (desc.nDesc == nDesc)
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{
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nCache = desc.nCacheSize;
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nCacheDesc = nDesc;
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break;
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}
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}
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}
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// See "Output of the CPUID instruction" from Intel, page 26.
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static void InterpretIntelCacheDescriptors(uint32_t nPackedDesc, CPUInformation& pi)
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{
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if (nPackedDesc & 0x80000000)
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{
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return; // This is a wrong descriptor.
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}
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for (int i = 0; i < 4; ++i)
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{
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uint8_t nDesc = nPackedDesc & 0xFF;
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FindIntelCacheDesc(nDesc, s_IntelL1DataCacheDesc, ARRAYSIZE(s_IntelL1DataCacheDesc), pi.m_nL1CacheSizeKb, pi.m_nL1CacheDesc);
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FindIntelCacheDesc(nDesc, s_IntelL2DataCacheDesc, ARRAYSIZE(s_IntelL2DataCacheDesc), pi.m_nL2CacheSizeKb, pi.m_nL2CacheDesc);
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FindIntelCacheDesc(nDesc, s_IntelL3DataCacheDesc, ARRAYSIZE(s_IntelL3DataCacheDesc), pi.m_nL3CacheSizeKb, pi.m_nL3CacheDesc);
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int nFamily = (pi.m_nModel >> 8) & 0xF;
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int nModel = (pi.m_nModel >> 4) & 0xF;
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if (nDesc == 0x49 && (nFamily != 0x0F || nModel != 0x06))
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{
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pi.m_nL3CacheSizeKb = 0;
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pi.m_nL3CacheDesc = 0;
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}
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nPackedDesc >>= 8;
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}
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}
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const CPUInformation& GetCPUInformation(void)
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{
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CPUInformation& pi = s_cpuInformation;
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// Has the structure already been initialized and filled out?
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if (pi.m_Size == sizeof(pi))
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{
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return pi;
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}
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// Redundant, but just in case the user somehow messes with the size.
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memset(&pi, 0x0, sizeof(pi));
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// Fill out the structure, and return it:
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pi.m_Size = sizeof(pi);
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// Grab the processor frequency:
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pi.m_Speed = CalculateClockSpeed();
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// Get the logical and physical processor counts:
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//pi.m_nLogicalProcessors = LogicalProcessorsPerPackage();
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bool bAuthenticAMD = (0 == _stricmp(GetProcessorVendorId(), "AuthenticAMD"));
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bool bGenuineIntel = !bAuthenticAMD && (0 == _stricmp(GetProcessorVendorId(), "GenuineIntel"));
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SYSTEM_INFO si;
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ZeroMemory(&si, sizeof(si));
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GetSystemInfo(&si);
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// Fixing: si.dwNumberOfProcessors is the number of logical processors according to experiments on i7, P4 and a DirectX sample (Aug'09).
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// This is contrary to MSDN documentation on GetSystemInfo().
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pi.m_nLogicalProcessors = uint8_t(si.dwNumberOfProcessors);
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CpuTopology topo;
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pi.m_nPhysicalProcessors = uint8_t(topo.NumberOfSystemCores());
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// Make sure I always report at least one, when running WinXP with the /ONECPU switch,
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// it likes to report 0 processors for some reason.
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if (pi.m_nPhysicalProcessors == 0 && pi.m_nLogicalProcessors == 0)
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{
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assert(!"Missing CPU detection code for this processor.");
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pi.m_nPhysicalProcessors = 1;
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pi.m_nLogicalProcessors = 1;
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}
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CpuIdResult_t cpuid0 = cpuid(0);
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if (cpuid0.eax >= 1)
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{
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CpuIdResult_t cpuid1 = cpuid(1);
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uint32_t bFPU = cpuid1.edx & 1; // This should always be set on anything we support.
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// Determine Processor Features:
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pi.m_bRDTSC = (cpuid1.edx >> 4) & 1;
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pi.m_bCMOV = (cpuid1.edx >> 15) & 1;
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pi.m_bFCMOV = (pi.m_bCMOV && bFPU) ? 1 : 0;
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pi.m_bMMX = (cpuid1.edx >> 23) & 1;
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pi.m_bSSE = (cpuid1.edx >> 25) & 1;
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pi.m_bSSE2 = (cpuid1.edx >> 26) & 1;
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pi.m_bSSE3 = cpuid1.ecx & 1;
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pi.m_bSSSE3 = (cpuid1.ecx >> 9) & 1;
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pi.m_bSSE4a = CheckSSE4aTechnology();
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pi.m_bSSE41 = (cpuid1.ecx >> 19) & 1;
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pi.m_bSSE42 = (cpuid1.ecx >> 20) & 1;
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pi.m_b3DNow = Check3DNowTechnology();
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pi.m_bAVX = (cpuid1.ecx >> 28) & 1;
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pi.m_szProcessorID = const_cast<char*>(GetProcessorVendorId());
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pi.m_szProcessorBrand = const_cast<char*>(GetProcessorBrand());
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pi.m_bHT = (pi.m_nPhysicalProcessors < pi.m_nLogicalProcessors); //HTSupported();
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pi.m_nModel = cpuid1.eax; // Full CPU model info.
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pi.m_nFeatures[0] = cpuid1.edx; // x87+ features.
|
|
pi.m_nFeatures[1] = cpuid1.ecx; // sse3+ features.
|
|
pi.m_nFeatures[2] = cpuid1.ebx; // Some additional features.
|
|
|
|
if (bGenuineIntel)
|
|
{
|
|
if (cpuid0.eax >= 4)
|
|
{
|
|
// We have CPUID.4, use it to find all the cache parameters.
|
|
const uint32_t nCachesToQuery = 4; // Level 0 is not used.
|
|
uint32_t nCacheSizeKiB[nCachesToQuery]{};
|
|
uint32_t nCacheDesc[nCachesToQuery]{};
|
|
|
|
for (unsigned long nSub = 0; nSub < 1024; ++nSub)
|
|
{
|
|
CpuIdResult_t cpuid4 = cpuidex(4, nSub);
|
|
uint32_t nCacheType = cpuid4.eax & 0x1F;
|
|
if (nCacheType == 0)
|
|
{
|
|
// No more caches.
|
|
break;
|
|
}
|
|
if (nCacheType & 1)
|
|
{
|
|
// This cache includes data cache: it's either data or unified. Instruction cache type is 2.
|
|
uint32_t nCacheLevel = (cpuid4.eax >> 5) & 7;
|
|
if (nCacheLevel < nCachesToQuery)
|
|
{
|
|
uint32_t nCacheWays = 1 + ((cpuid4.ebx >> 22) & 0x3F);
|
|
uint32_t nCachePartitions = 1 + ((cpuid4.ebx >> 12) & 0x3F);
|
|
uint32_t nCacheLineSize = 1 + (cpuid4.ebx & 0xFF);
|
|
uint32_t nCacheSets = 1 + cpuid4.ecx;
|
|
uint32_t nCacheSizeBytes = nCacheWays * nCachePartitions * nCacheLineSize * nCacheSets;
|
|
|
|
nCacheSizeKiB[nCacheLevel] = nCacheSizeBytes >> 10;
|
|
nCacheDesc[nCacheLevel] = 1 + cpuid4.ebx;
|
|
}
|
|
}
|
|
}
|
|
|
|
pi.m_nL1CacheSizeKb = nCacheSizeKiB[1];
|
|
pi.m_nL1CacheDesc = nCacheDesc[1];
|
|
pi.m_nL2CacheSizeKb = nCacheSizeKiB[2];
|
|
pi.m_nL2CacheDesc = nCacheDesc[2];
|
|
pi.m_nL3CacheSizeKb = nCacheSizeKiB[3];
|
|
pi.m_nL3CacheDesc = nCacheDesc[3];
|
|
}
|
|
else if (cpuid0.eax >= 2)
|
|
{
|
|
// Get the cache.
|
|
CpuIdResult_t cpuid2 = cpuid(2);
|
|
for (int i = (cpuid2.eax & 0xFF); i-- > 0; )
|
|
{
|
|
InterpretIntelCacheDescriptors(cpuid2.eax & ~0xFF, pi);
|
|
InterpretIntelCacheDescriptors(cpuid2.ebx, pi);
|
|
InterpretIntelCacheDescriptors(cpuid2.ecx, pi);
|
|
InterpretIntelCacheDescriptors(cpuid2.edx, pi);
|
|
cpuid2 = cpuid(2); // Read the next.
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
CpuIdResult_t cpuid0ex = cpuid(0x80000000);
|
|
if (bAuthenticAMD)
|
|
{
|
|
// TODO: add '0x8000001D' (newer AMD cpu's).
|
|
// Fall back to below if value doesn't equal/exceed it.
|
|
if (cpuid0ex.eax >= 0x80000005)
|
|
{
|
|
CpuIdResult_t cpuid5ex = cpuid(0x80000005);
|
|
pi.m_nL1CacheSizeKb = cpuid5ex.ecx >> 24;
|
|
pi.m_nL1CacheDesc = cpuid5ex.ecx & 0xFFFFFF;
|
|
}
|
|
if (cpuid0ex.eax >= 0x80000006)
|
|
{
|
|
CpuIdResult_t cpuid6ex = cpuid(0x80000006);
|
|
pi.m_nL2CacheSizeKb = cpuid6ex.ecx >> 16;
|
|
pi.m_nL2CacheDesc = cpuid6ex.ecx & 0xFFFF;
|
|
pi.m_nL3CacheSizeKb = (cpuid6ex.edx >> 18) * 512;
|
|
pi.m_nL3CacheDesc = cpuid6ex.edx & 0xFFFF;
|
|
}
|
|
}
|
|
else if (bGenuineIntel)
|
|
{
|
|
if (cpuid0ex.eax >= 0x80000006)
|
|
{
|
|
// Make sure we got the L2 cache info right.
|
|
CpuIdResult_t cpuid6ex = cpuid(0x80000006);
|
|
|
|
pi.m_nL2CacheSizeKb = cpuid6ex.ecx >> 16;
|
|
pi.m_nL2CacheDesc = cpuid6ex.ecx & 0xFFFF;
|
|
}
|
|
}
|
|
return pi;
|
|
}
|