Citra-emu/dynarmic-android
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Author SHA1 Message Date
SachinVin
0b81c5a3c1 backend/A64: Move SP to FP in GenMemoryAccessors + Minor cleanup and 2020-05-16 17:18:41 +05:30
SachinVin
941a6ba808 backend/A64: Use X26 for storing remaining cycles. 2020-05-16 17:18:41 +05:30
BreadFish64
eeb7c609fc backend/A64: add fastmem support 
fix crash on game close

fix generic exception handler

reorder hostloc gpr list

use temp register instead of X0 for writes

go back to regular std::partition
 2020-05-16 17:18:41 +05:30
BreadFish64
c4b62bb22e merge fastmem 2020-05-16 17:18:40 +05:30
SachinVin
2d7f2b11b2 backend\A64\constant_pool.cpp: Correct offset calculation 2020-05-16 17:18:40 +05:30
SachinVin
6a3c3579d1 backend/A64/a32_jitstate: Upstream changes from x64 backend 2020-05-16 17:18:40 +05:30
SachinVin
3db06be313 backend/A64: Add test for q flag being incorrectly set 2020-05-16 17:18:39 +05:30
SachinVin
d3e5bd4b43 backend/A64/a32_emit_a64.cpp: Use unused HostCall registers 2020-05-16 17:18:39 +05:30
SachinVin
5aa7b3cbed backend/A64/a32_emit_a64.cpp: Use MOVP2R instead of MOVI2R. 2020-05-16 17:18:39 +05:30
SachinVin
8fd3c5c4f3 backend/A64/abi: Fix FP caller and callee save registers 2020-05-16 17:18:39 +05:30
SachinVin
0f22688948 a64/block_of_code: use GetWritableCodePtr() instead of const_cast<...>(GetCodePtr()) 2020-05-16 17:18:38 +05:30
SachinVin
58450e7b42 backend/A64/constant_pool: Clean up unused stuff 2020-05-16 17:18:38 +05:30
SachinVin
c3dab59e46 emit_a64_data_processing.cpp: remove pointless DoNZCV. 2020-05-16 17:18:38 +05:30
SachinVin
351a557618 IR + backend/*: add SetCpsrNZCVRaw and change arg1 type of SetCpsrNZCV to IR::NZCV 2020-05-16 17:18:37 +05:30
SachinVin
75ed09b939 backend/A64: Fix ASR impl 2020-05-16 17:18:37 +05:30
SachinVin
fd4a8f277d a64_emitter: Use Correct alias for ZR and WZR in CMP 2020-05-16 17:18:37 +05:30
SachinVin
722e76f75f backend/A64: Use CSLE instead of branches for LSL LSR and ASR + minor cleanup 2020-05-16 17:18:36 +05:30
SachinVin
40463bde01 backend/A64: Use correct register size for EmitNot64 2020-05-16 17:18:36 +05:30
SachinVin
203e8326fc tests/A32: Check if Q flag is cleared properly 2020-05-16 17:18:35 +05:30
SachinVin
5a54320fea backend/A64: SignedSaturatedSub and SignedSaturatedAdd 2020-05-16 17:15:37 +05:30
SachinVin
571d3c49c9 backend/A64/emit_a64_saturation.cpp: Implement EmitSignedSaturation and EmitUnsignedSaturation 
Implements SSAT SSAT16 USAT USAT16 QASX QSAX UQASX UQSAX
 2020-05-16 17:15:37 +05:30
SachinVin
d61d21593f backend/A64: add emit_a64_saturation.cpp 2020-05-16 17:15:36 +05:30
SachinVin
1a295642fb backend/A64: Fix EmitA32SetCpsr 2020-05-16 17:15:36 +05:30
SachinVin
631274453a backend/A64/devirtualize: remove unused DevirtualizeItanium 2020-05-16 17:15:35 +05:30
SachinVin
d815a9bd08 backend/A64: refactor to fpscr from mxcsr 2020-05-16 17:15:35 +05:30
SachinVin
e06008a530 backend/A64: Use ScratchGpr() instead of ABI_SCRATCH1 where possible 2020-05-16 17:15:35 +05:30
SachinVin
3c30758dca backend/A64: support for always_little_endian 2020-05-16 17:15:35 +05:30
SachinVin
1a32b5501c backend/a64: Add hook_hint_instructions option 
534eb0f
 2020-05-16 17:15:34 +05:30
SachinVin
0d05eeb90a backend /A64: cleanup 2020-05-16 17:15:34 +05:30
SachinVin
14b94212a8 gitignore: add .vs dir 2020-05-16 17:15:34 +05:30
SachinVin
6faf2816bc Minor style fix 2020-05-16 17:15:34 +05:30
SachinVin
e45461ef9f backend\A64\emit_a64_packed.cpp: Implement AddSub halving and non halving 2020-05-16 17:15:33 +05:30
SachinVin
4880a6cfa7 backend\A64: Instructions that got implemented on the way 2020-05-16 17:15:33 +05:30
SachinVin
04a59768c6 backend\A64\emit_a64_packed.cpp: Implement Unsigned Sum of Absolute Differences 2020-05-16 17:15:32 +05:30
SachinVin
6ba3bbf7d4 a64 emitter: Absolute Difference and add across vector instructions 2020-05-16 17:15:32 +05:30
SachinVin
8216b2f7aa backend\A64\emit_a64_packed.cpp: Implement Packed Select 2020-05-16 17:15:32 +05:30
SachinVin
f889ecaf4d Backend/a64: Fix asset when falling back to interpreter 2020-05-16 17:15:31 +05:30
SachinVin
340e772c1f backend\A64\emit_a64_packed.cpp: Implement Packed Halving Add/Sub instructions 2020-05-16 17:15:31 +05:30
SachinVin
9e0a3e7aa0 backend\A64\emit_a64_packed.cpp: Implement Packed Saturating instructions 2020-05-16 17:15:30 +05:30
SachinVin
79157ef109 backend\A64\emit_a64_packed.cpp: Implement SignedPacked*- ADD and SUB 2020-05-16 17:15:30 +05:30
SachinVin
3ed0a9a593 a64 emitter: Vector Halving and Saturation instructions 2020-05-16 17:15:30 +05:30
SachinVin
42d5e1bc0e backend\A64\emit_a64_packed.cpp: Implement UnsignedPacked*- ADD and SUB... 
with few other in the emitter
 2020-05-16 17:15:29 +05:30
SachinVin
c78aa47c00 a64 emitter: fix Scalar Saturating Instructions 2020-05-16 17:15:29 +05:30
SachinVin
cc19981999 A64 Emitter: Implement Saturating Add and Sub 2020-05-16 17:15:29 +05:30
SachinVin
45a6d5d025 backend\A64\emit_a64_data_processing.cpp: Implement Division 2020-05-16 17:15:28 +05:30
SachinVin
3910b7b1bb backend\A64\emit_a64_data_processing.cpp: Implement 64bit CLZ 2020-05-16 17:15:28 +05:30
SachinVin
33f0c18ea4 backend\A64\emit_a64_data_processing.cpp: Implement 64bit LSL and ROR Instructions 
Also EmitTestBit
 2020-05-16 17:15:28 +05:30
SachinVin
69295c4918 backend\A64\emit_a64_data_processing.cpp: Implement 64bit Logical Instructions 2020-05-16 17:15:27 +05:30
SachinVin
745a924106 backend/a64: implememnt CheckBit 2020-05-16 17:15:27 +05:30
SachinVin
e27809706a backend/a64: Redesign Const Pool 2020-05-16 17:15:27 +05:30