SachinVin
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3d4caa5ee1
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backend /A64: cleanup
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2020-05-23 19:54:57 +05:30 |
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SachinVin
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d027786e4e
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gitignore: add .vs dir
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2020-05-23 19:54:57 +05:30 |
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SachinVin
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0c7e261aac
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Minor style fix
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2020-05-23 19:54:57 +05:30 |
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SachinVin
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6b167a68e4
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backend\A64\emit_a64_packed.cpp: Implement AddSub halving and non halving
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2020-05-23 19:54:56 +05:30 |
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SachinVin
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a87b13cabf
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backend\A64: Instructions that got implemented on the way
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2020-05-23 19:54:56 +05:30 |
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SachinVin
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17e64406aa
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backend\A64\emit_a64_packed.cpp: Implement Unsigned Sum of Absolute Differences
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2020-05-23 19:54:55 +05:30 |
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SachinVin
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871617ac3b
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a64 emitter: Absolute Difference and add across vector instructions
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2020-05-23 19:54:55 +05:30 |
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SachinVin
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f9ba12a9e6
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backend\A64\emit_a64_packed.cpp: Implement Packed Select
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2020-05-23 19:54:54 +05:30 |
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SachinVin
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607a3c7110
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Backend/a64: Fix asset when falling back to interpreter
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2020-05-23 19:54:54 +05:30 |
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SachinVin
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a5564f588d
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backend\A64\emit_a64_packed.cpp: Implement Packed Halving Add/Sub instructions
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2020-05-23 19:54:53 +05:30 |
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SachinVin
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fd01d6fe0a
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backend\A64\emit_a64_packed.cpp: Implement Packed Saturating instructions
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2020-05-23 19:54:53 +05:30 |
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SachinVin
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b4fb2569ad
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backend\A64\emit_a64_packed.cpp: Implement SignedPacked*- ADD and SUB
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2020-05-23 19:54:52 +05:30 |
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SachinVin
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8f98852249
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a64 emitter: Vector Halving and Saturation instructions
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2020-05-23 19:54:52 +05:30 |
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SachinVin
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9059505a2f
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backend\A64\emit_a64_packed.cpp: Implement UnsignedPacked*- ADD and SUB...
with few other in the emitter
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2020-05-23 19:54:51 +05:30 |
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SachinVin
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5ad5784ef8
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a64 emitter: fix Scalar Saturating Instructions
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2020-05-23 19:54:51 +05:30 |
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SachinVin
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f0eee83098
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A64 Emitter: Implement Saturating Add and Sub
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2020-05-23 19:54:50 +05:30 |
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SachinVin
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ebd185968d
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backend\A64\emit_a64_data_processing.cpp: Implement Division
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2020-05-23 19:54:50 +05:30 |
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SachinVin
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def0137021
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backend\A64\emit_a64_data_processing.cpp: Implement 64bit CLZ
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2020-05-23 19:54:50 +05:30 |
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SachinVin
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9f227edfe4
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backend\A64\emit_a64_data_processing.cpp: Implement 64bit LSL and ROR Instructions
Also EmitTestBit
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2020-05-23 19:54:49 +05:30 |
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SachinVin
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bb70cdd28c
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backend\A64\emit_a64_data_processing.cpp: Implement 64bit Logical Instructions
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2020-05-23 19:54:49 +05:30 |
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SachinVin
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f851695f51
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backend/a64: implememnt CheckBit
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2020-05-23 19:54:49 +05:30 |
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SachinVin
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6d25995375
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backend/a64: Redesign Const Pool
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2020-05-23 19:54:48 +05:30 |
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SachinVin
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410c2010e9
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backend\A64\emit_a64_floating_point.cpp: Fix include paths
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2020-05-23 19:54:48 +05:30 |
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SachinVin
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8e3ad2feb5
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backend\A64\a32_emit_a64.cpp: Fix Coproc* after rebase
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2020-05-23 19:54:48 +05:30 |
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SachinVin
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fe49607add
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backend/a64/opcodes.inc: Coproc instructions
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2020-05-23 19:54:47 +05:30 |
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SachinVin
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324e3c1fd1
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a64 emitter: Fix LDR literal
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2020-05-23 19:54:47 +05:30 |
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SachinVin
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3f220d94c6
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a64 emitter: Move IsInRange* and MaskImm* into anon namespace
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2020-05-23 19:54:47 +05:30 |
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SachinVin
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410dcf87a5
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backend\A64\emit_a64_floating_point.cpp: Implement VADD VSUB VMUL and other stuff
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2020-05-23 19:54:46 +05:30 |
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SachinVin
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4459188bfc
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backend\A64\emit_a64_floating_point.cpp: Implement VABS VNEG VCMP and a few others
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2020-05-23 19:54:46 +05:30 |
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SachinVin
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23dc3cee01
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frontend/A32/Decoder : (backend/a64)VMOV
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2020-05-23 19:54:45 +05:30 |
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SachinVin
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72c8e5e536
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backend\A64\emit_a64_floating_point.cpp: Implement VCVT instructions
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2020-05-23 19:54:45 +05:30 |
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SachinVin
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50301cffbd
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backend\A64\emit_a64_floating_point.cpp: part 1
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2020-05-23 19:54:44 +05:30 |
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SachinVin
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62f7b030e1
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backend/a64/reg_alloc: Fix EmitMove for FPRs
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2020-05-23 19:54:44 +05:30 |
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SachinVin
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b92195f2ae
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A64 emitter: Support for 64bit FMOV
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2020-05-23 19:54:44 +05:30 |
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SachinVin
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1bd416aefb
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a64 backend: Load "guest_FPSR"
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2020-05-23 19:54:43 +05:30 |
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SachinVin
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7661987e04
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A64 backend: Add Get/SetExtendedRegister and Get/SetGEFlags
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2020-05-23 19:54:43 +05:30 |
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SachinVin
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1a59aaec11
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tests: Dont compile A64 tests for non x64 backend
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2020-05-23 19:54:43 +05:30 |
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SachinVin
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952eb5c83f
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travis a64: unicorn
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2020-05-23 19:54:43 +05:30 |
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SachinVin
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1c9ac3284e
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travis a64 backend
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2020-05-23 19:54:42 +05:30 |
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SachinVin
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4da93c3130
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Frontend/A32: a64 backend; Interpret SEL
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2020-05-23 19:54:42 +05:30 |
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SachinVin
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8106f2a81b
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frontend/A32: A64 Backend implemented instructions
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2020-05-23 19:54:42 +05:30 |
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SachinVin
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db07bfa933
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backend\A64\emit_a64_data_processing.cpp: Implement REV and CLZ ops
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2020-05-23 19:54:41 +05:30 |
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SachinVin
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6835cf34a1
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backend\A64\emit_a64_data_processing.cpp: Implement Sext an Zext ops
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2020-05-23 19:54:41 +05:30 |
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SachinVin
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e3054389a6
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backend\A64\emit_a64_data_processing.cpp: Implement Logical ops
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2020-05-23 19:54:40 +05:30 |
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SachinVin
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d37ec336a4
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backend\A64\emit_a64_data_processing.cpp: Implement Arithmetic ops
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2020-05-23 19:54:40 +05:30 |
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SachinVin
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e086d0df7f
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backend\A64\emit_a64_data_processing.cpp: Implement Shift and Rotate ops
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2020-05-23 19:54:40 +05:30 |
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SachinVin
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8781a0f184
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backend\A64\emit_a64_data_processing.cpp:Implement ops
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2020-05-23 19:54:39 +05:30 |
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SachinVin
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a66bcdfc91
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backend\A64\emit_a64_data_processing.cpp: Mostly empty file
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2020-05-23 19:54:39 +05:30 |
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SachinVin
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9df55fc951
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backend/a64: Add a32_interface
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2020-05-23 19:54:38 +05:30 |
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SachinVin
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cb56c74d19
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backend/a64: Port a32_emit_a64
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2020-05-23 19:54:38 +05:30 |
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