Citra-emu/dynarmic-android
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Author SHA1 Message Date
SachinVin
43d37293b1 backend/A64: Fix ASR impl 2020-05-23 19:55:01 +05:30
SachinVin
e12d635bde a64_emitter: Use Correct alias for ZR and WZR in CMP 2020-05-23 19:55:01 +05:30
SachinVin
8c66a1609e backend/A64: Use CSLE instead of branches for LSL LSR and ASR + minor cleanup 2020-05-23 19:55:01 +05:30
SachinVin
878db6d65d backend/A64: Use correct register size for EmitNot64 2020-05-23 19:55:01 +05:30
SachinVin
f8594f3bb9 tests/A32: Check if Q flag is cleared properly 2020-05-23 19:55:00 +05:30
SachinVin
296bbdd0b0 backend/A64: SignedSaturatedSub and SignedSaturatedAdd 2020-05-23 19:55:00 +05:30
SachinVin
a6c2d1952a backend/A64/emit_a64_saturation.cpp: Implement EmitSignedSaturation and EmitUnsignedSaturation 
Implements SSAT SSAT16 USAT USAT16 QASX QSAX UQASX UQSAX
 2020-05-23 19:55:00 +05:30
SachinVin
011d62d958 backend/A64: add emit_a64_saturation.cpp 2020-05-23 19:54:59 +05:30
SachinVin
ad59325b45 backend/A64: Fix EmitA32SetCpsr 2020-05-23 19:54:59 +05:30
SachinVin
61ea47ad7b backend/A64/devirtualize: remove unused DevirtualizeItanium 2020-05-23 19:54:59 +05:30
SachinVin
bb39f419e2 backend/A64: refactor to fpscr from mxcsr 2020-05-23 19:54:58 +05:30
SachinVin
47c0632e16 backend/A64: Use ScratchGpr() instead of ABI_SCRATCH1 where possible 2020-05-23 19:54:58 +05:30
SachinVin
60303dbfa8 backend/A64: support for always_little_endian 2020-05-23 19:54:58 +05:30
SachinVin
19cd6f0309 backend/a64: Add hook_hint_instructions option 
534eb0f
 2020-05-23 19:54:57 +05:30
SachinVin
3d4caa5ee1 backend /A64: cleanup 2020-05-23 19:54:57 +05:30
SachinVin
d027786e4e gitignore: add .vs dir 2020-05-23 19:54:57 +05:30
SachinVin
0c7e261aac Minor style fix 2020-05-23 19:54:57 +05:30
SachinVin
6b167a68e4 backend\A64\emit_a64_packed.cpp: Implement AddSub halving and non halving 2020-05-23 19:54:56 +05:30
SachinVin
a87b13cabf backend\A64: Instructions that got implemented on the way 2020-05-23 19:54:56 +05:30
SachinVin
17e64406aa backend\A64\emit_a64_packed.cpp: Implement Unsigned Sum of Absolute Differences 2020-05-23 19:54:55 +05:30
SachinVin
871617ac3b a64 emitter: Absolute Difference and add across vector instructions 2020-05-23 19:54:55 +05:30
SachinVin
f9ba12a9e6 backend\A64\emit_a64_packed.cpp: Implement Packed Select 2020-05-23 19:54:54 +05:30
SachinVin
607a3c7110 Backend/a64: Fix asset when falling back to interpreter 2020-05-23 19:54:54 +05:30
SachinVin
a5564f588d backend\A64\emit_a64_packed.cpp: Implement Packed Halving Add/Sub instructions 2020-05-23 19:54:53 +05:30
SachinVin
fd01d6fe0a backend\A64\emit_a64_packed.cpp: Implement Packed Saturating instructions 2020-05-23 19:54:53 +05:30
SachinVin
b4fb2569ad backend\A64\emit_a64_packed.cpp: Implement SignedPacked*- ADD and SUB 2020-05-23 19:54:52 +05:30
SachinVin
8f98852249 a64 emitter: Vector Halving and Saturation instructions 2020-05-23 19:54:52 +05:30
SachinVin
9059505a2f backend\A64\emit_a64_packed.cpp: Implement UnsignedPacked*- ADD and SUB... 
with few other in the emitter
 2020-05-23 19:54:51 +05:30
SachinVin
5ad5784ef8 a64 emitter: fix Scalar Saturating Instructions 2020-05-23 19:54:51 +05:30
SachinVin
f0eee83098 A64 Emitter: Implement Saturating Add and Sub 2020-05-23 19:54:50 +05:30
SachinVin
ebd185968d backend\A64\emit_a64_data_processing.cpp: Implement Division 2020-05-23 19:54:50 +05:30
SachinVin
def0137021 backend\A64\emit_a64_data_processing.cpp: Implement 64bit CLZ 2020-05-23 19:54:50 +05:30
SachinVin
9f227edfe4 backend\A64\emit_a64_data_processing.cpp: Implement 64bit LSL and ROR Instructions 
Also EmitTestBit
 2020-05-23 19:54:49 +05:30
SachinVin
bb70cdd28c backend\A64\emit_a64_data_processing.cpp: Implement 64bit Logical Instructions 2020-05-23 19:54:49 +05:30
SachinVin
f851695f51 backend/a64: implememnt CheckBit 2020-05-23 19:54:49 +05:30
SachinVin
6d25995375 backend/a64: Redesign Const Pool 2020-05-23 19:54:48 +05:30
SachinVin
410c2010e9 backend\A64\emit_a64_floating_point.cpp: Fix include paths 2020-05-23 19:54:48 +05:30
SachinVin
8e3ad2feb5 backend\A64\a32_emit_a64.cpp: Fix Coproc* after rebase 2020-05-23 19:54:48 +05:30
SachinVin
fe49607add backend/a64/opcodes.inc: Coproc instructions 2020-05-23 19:54:47 +05:30
SachinVin
324e3c1fd1 a64 emitter: Fix LDR literal 2020-05-23 19:54:47 +05:30
SachinVin
3f220d94c6 a64 emitter: Move IsInRange* and MaskImm* into anon namespace 2020-05-23 19:54:47 +05:30
SachinVin
410dcf87a5 backend\A64\emit_a64_floating_point.cpp: Implement VADD VSUB VMUL and other stuff 2020-05-23 19:54:46 +05:30
SachinVin
4459188bfc backend\A64\emit_a64_floating_point.cpp: Implement VABS VNEG VCMP and a few others 2020-05-23 19:54:46 +05:30
SachinVin
23dc3cee01 frontend/A32/Decoder : (backend/a64)VMOV 2020-05-23 19:54:45 +05:30
SachinVin
72c8e5e536 backend\A64\emit_a64_floating_point.cpp: Implement VCVT instructions 2020-05-23 19:54:45 +05:30
SachinVin
50301cffbd backend\A64\emit_a64_floating_point.cpp: part 1 2020-05-23 19:54:44 +05:30
SachinVin
62f7b030e1 backend/a64/reg_alloc: Fix EmitMove for FPRs 2020-05-23 19:54:44 +05:30
SachinVin
b92195f2ae A64 emitter: Support for 64bit FMOV 2020-05-23 19:54:44 +05:30
SachinVin
1bd416aefb a64 backend: Load "guest_FPSR" 2020-05-23 19:54:43 +05:30
SachinVin
7661987e04 A64 backend: Add Get/SetExtendedRegister and Get/SetGEFlags 2020-05-23 19:54:43 +05:30