SachinVin
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6ba3bbf7d4
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a64 emitter: Absolute Difference and add across vector instructions
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2020-05-16 17:15:32 +05:30 |
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SachinVin
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8216b2f7aa
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backend\A64\emit_a64_packed.cpp: Implement Packed Select
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2020-05-16 17:15:32 +05:30 |
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SachinVin
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f889ecaf4d
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Backend/a64: Fix asset when falling back to interpreter
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2020-05-16 17:15:31 +05:30 |
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SachinVin
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340e772c1f
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backend\A64\emit_a64_packed.cpp: Implement Packed Halving Add/Sub instructions
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2020-05-16 17:15:31 +05:30 |
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SachinVin
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9e0a3e7aa0
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backend\A64\emit_a64_packed.cpp: Implement Packed Saturating instructions
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2020-05-16 17:15:30 +05:30 |
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SachinVin
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79157ef109
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backend\A64\emit_a64_packed.cpp: Implement SignedPacked*- ADD and SUB
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2020-05-16 17:15:30 +05:30 |
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SachinVin
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3ed0a9a593
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a64 emitter: Vector Halving and Saturation instructions
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2020-05-16 17:15:30 +05:30 |
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SachinVin
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42d5e1bc0e
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backend\A64\emit_a64_packed.cpp: Implement UnsignedPacked*- ADD and SUB...
with few other in the emitter
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2020-05-16 17:15:29 +05:30 |
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SachinVin
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c78aa47c00
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a64 emitter: fix Scalar Saturating Instructions
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2020-05-16 17:15:29 +05:30 |
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SachinVin
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cc19981999
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A64 Emitter: Implement Saturating Add and Sub
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2020-05-16 17:15:29 +05:30 |
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SachinVin
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45a6d5d025
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backend\A64\emit_a64_data_processing.cpp: Implement Division
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2020-05-16 17:15:28 +05:30 |
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SachinVin
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3910b7b1bb
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backend\A64\emit_a64_data_processing.cpp: Implement 64bit CLZ
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2020-05-16 17:15:28 +05:30 |
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SachinVin
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33f0c18ea4
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backend\A64\emit_a64_data_processing.cpp: Implement 64bit LSL and ROR Instructions
Also EmitTestBit
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2020-05-16 17:15:28 +05:30 |
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SachinVin
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69295c4918
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backend\A64\emit_a64_data_processing.cpp: Implement 64bit Logical Instructions
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2020-05-16 17:15:27 +05:30 |
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SachinVin
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745a924106
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backend/a64: implememnt CheckBit
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2020-05-16 17:15:27 +05:30 |
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SachinVin
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e27809706a
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backend/a64: Redesign Const Pool
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2020-05-16 17:15:27 +05:30 |
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SachinVin
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42873f0825
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backend\A64\emit_a64_floating_point.cpp: Fix include paths
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2020-05-16 17:15:26 +05:30 |
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SachinVin
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07f648d906
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backend\A64\a32_emit_a64.cpp: Fix Coproc* after rebase
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2020-05-16 17:15:26 +05:30 |
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SachinVin
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1de1bdb6d4
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backend/a64/opcodes.inc: Coproc instructions
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2020-05-16 17:15:26 +05:30 |
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SachinVin
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47a2441640
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a64 emitter: Fix LDR literal
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2020-05-16 17:15:25 +05:30 |
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SachinVin
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1a9bdd41ea
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a64 emitter: Move IsInRange* and MaskImm* into anon namespace
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2020-05-16 17:15:25 +05:30 |
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SachinVin
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be3ba643cc
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backend\A64\emit_a64_floating_point.cpp: Implement VADD VSUB VMUL and other stuff
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2020-05-16 17:15:25 +05:30 |
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SachinVin
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9c789ded58
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backend\A64\emit_a64_floating_point.cpp: Implement VABS VNEG VCMP and a few others
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2020-05-16 17:15:24 +05:30 |
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SachinVin
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bb9ed1c4ec
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frontend/A32/Decoder : (backend/a64)VMOV
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2020-05-16 17:15:24 +05:30 |
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SachinVin
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967c4e93b7
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backend\A64\emit_a64_floating_point.cpp: Implement VCVT instructions
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2020-05-16 17:15:24 +05:30 |
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SachinVin
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86e0ab0836
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backend\A64\emit_a64_floating_point.cpp: part 1
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2020-05-16 17:15:23 +05:30 |
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SachinVin
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dda7b5013a
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backend/a64/reg_alloc: Fix EmitMove for FPRs
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2020-05-16 17:15:23 +05:30 |
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SachinVin
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7bfc973efe
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A64 emitter: Support for 64bit FMOV
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2020-05-16 17:15:22 +05:30 |
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SachinVin
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c97c18f64b
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a64 backend: Load "guest_FPSR"
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2020-05-16 17:15:22 +05:30 |
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SachinVin
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32eba73e1e
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A64 backend: Add Get/SetExtendedRegister and Get/SetGEFlags
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2020-05-16 17:15:22 +05:30 |
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SachinVin
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c64e2812a8
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tests: Dont compile A64 tests for non x64 backend
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2020-05-16 17:15:22 +05:30 |
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SachinVin
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ea2be0b7ef
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travis a64: unicorn
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2020-05-16 17:15:21 +05:30 |
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SachinVin
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a00248bd27
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travis a64 backend
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2020-05-16 17:15:21 +05:30 |
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SachinVin
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54dbfe86da
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Frontend/A32: a64 backend; Interpret SEL
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2020-05-16 17:15:20 +05:30 |
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SachinVin
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cafe0c8d65
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frontend/A32: A64 Backend implemented instructions
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2020-05-16 17:15:20 +05:30 |
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SachinVin
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563dfded57
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backend\A64\emit_a64_data_processing.cpp: Implement REV and CLZ ops
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2020-05-16 17:15:19 +05:30 |
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SachinVin
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dddba6b9f5
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backend\A64\emit_a64_data_processing.cpp: Implement Sext an Zext ops
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2020-05-16 17:15:19 +05:30 |
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SachinVin
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401432b922
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backend\A64\emit_a64_data_processing.cpp: Implement Logical ops
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2020-05-16 17:15:19 +05:30 |
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SachinVin
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96a7171126
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backend\A64\emit_a64_data_processing.cpp: Implement Arithmetic ops
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2020-05-16 17:15:19 +05:30 |
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SachinVin
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21e59707ed
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backend\A64\emit_a64_data_processing.cpp: Implement Shift and Rotate ops
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2020-05-16 17:15:18 +05:30 |
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SachinVin
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1fa8c36ab1
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backend\A64\emit_a64_data_processing.cpp:Implement ops
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2020-05-16 17:15:18 +05:30 |
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SachinVin
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a2c44e9a27
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backend\A64\emit_a64_data_processing.cpp: Mostly empty file
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2020-05-16 17:15:18 +05:30 |
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SachinVin
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9301cf2273
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backend/a64: Add a32_interface
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2020-05-16 17:15:17 +05:30 |
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SachinVin
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b4513f152a
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backend/a64: Port a32_emit_a64
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2020-05-16 17:15:17 +05:30 |
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SachinVin
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3e655508b5
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backend/a64: Port block_of_code and emit_a64
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2020-05-16 17:15:17 +05:30 |
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SachinVin
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544988c1f4
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backend/a64: Port callback functions
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2020-05-16 17:15:17 +05:30 |
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SachinVin
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4b53c90bfb
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backend/a64: Port exception handler
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2020-05-16 17:15:16 +05:30 |
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SachinVin
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53056f0a95
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backend/a64: Port const pool
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2020-05-16 17:15:16 +05:30 |
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SachinVin
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0e5e9759b6
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backend/a64: Port reg_alloc
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2020-05-16 17:15:16 +05:30 |
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SachinVin
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b06c8acce4
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backend/a64: Port ABI functions
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2020-05-16 17:15:15 +05:30 |
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