MerryMage
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b277bf5061
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Correct FPSR and FPCR
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2018-02-20 20:31:17 +00:00 |
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MerryMage
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7673933a9b
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A64: Implement USHL
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2018-02-20 19:48:15 +00:00 |
|
MerryMage
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8d0e558271
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A64: Implement UCVTF (vector, integer), scalar variant
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2018-02-20 19:11:35 +00:00 |
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MerryMage
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da9a4f8877
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A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
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2018-02-20 18:45:28 +00:00 |
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MerryMage
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747968416f
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A64: Implement system register TPIDR_EL0
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2018-02-20 17:56:20 +00:00 |
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MerryMage
|
0fd75fd9cb
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A64: Implement system registers FPCR and FPSR
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2018-02-20 17:38:29 +00:00 |
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MerryMage
|
31e370cdf4
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A64: Implement system register CNTPCT_EL0
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2018-02-20 16:56:05 +00:00 |
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MerryMage
|
9a88fd3340
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A64: Implement system register CTR_EL0
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2018-02-20 16:44:13 +00:00 |
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MerryMage
|
1d16896d25
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A64: Implement NEG (vector)
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2018-02-20 15:41:07 +00:00 |
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MerryMage
|
3184edf4a9
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IR: Add IR instruction ZeroVector
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2018-02-20 15:41:07 +00:00 |
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MerryMage
|
567eb1a2f1
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A64: Implement FMINNM (scalar)
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2018-02-20 14:14:40 +00:00 |
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MerryMage
|
c6d8fa1d36
|
A64: Implement FMAXNM (scalar)
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2018-02-20 14:05:14 +00:00 |
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MerryMage
|
a3747cb01c
|
A64: Implement ADDP (scalar)
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2018-02-18 23:55:38 +00:00 |
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MerryMage
|
dd0452a435
|
A64: Implement DUP (element), scalar variant
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2018-02-18 18:58:01 +00:00 |
|
MerryMage
|
40eb9c3253
|
A64: Implement FMAX (scalar), FMIN (scalar)
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2018-02-18 13:49:23 +00:00 |
|
MerryMage
|
be292a819c
|
A64: Implement FSQRT (scalar)
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2018-02-18 13:18:22 +00:00 |
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MerryMage
|
e585e1d49e
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T32: Add initial decoder list
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2018-02-14 19:29:19 +00:00 |
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MerryMage
|
1598af4f12
|
simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector)
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2018-02-13 19:01:47 +00:00 |
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MerryMage
|
029ae11040
|
A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero)
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2018-02-13 19:01:21 +00:00 |
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MerryMage
|
91483ab975
|
decoder/a64: Rearrange SIMD two-register misc decoders
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2018-02-13 18:51:43 +00:00 |
|
MerryMage
|
9158534048
|
A64: Implement CMGE (register)
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2018-02-13 18:29:54 +00:00 |
|
MerryMage
|
41e421bf0b
|
A64: Implement CMHI, CMHS
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2018-02-13 18:20:18 +00:00 |
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MerryMage
|
324810cfad
|
IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
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2018-02-13 18:20:00 +00:00 |
|
MerryMage
|
89007194a7
|
A64: Implement SMAX, SMIN, UMAX, UMIN
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2018-02-13 17:57:07 +00:00 |
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MerryMage
|
2880eb3da1
|
IR: Implement Vector{Max,Min}{Signed,Unsigned}
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2018-02-13 17:56:46 +00:00 |
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MerryMage
|
7d8543b70e
|
A64: Implement CMGT (register)
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2018-02-13 15:47:52 +00:00 |
|
MerryMage
|
6d4f14e876
|
IR: Implement VectorGreaterSigned
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2018-02-13 15:47:52 +00:00 |
|
MerryMage
|
9527d52c49
|
Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
|
2018-02-13 15:47:52 +00:00 |
|
MerryMage
|
229ff47738
|
Merge branch 'feature/exclusive-mem'
|
2018-02-13 12:53:29 +00:00 |
|
MerryMage
|
43f27b3e15
|
A64: Implement STXP, STLXP, LDXP, LDAXP
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2018-02-13 12:50:50 +00:00 |
|
MerryMage
|
11eb8c2bea
|
A64: Implement CLREX
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2018-02-13 12:31:16 +00:00 |
|
MerryMage
|
22285842af
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
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2018-02-13 12:30:58 +00:00 |
|
MerryMage
|
7a161ed35c
|
A64: Partially implement MRS
|
2018-02-12 00:06:44 +00:00 |
|
MerryMage
|
b733479b5e
|
A64: Implement DSB, DMB
|
2018-02-11 23:27:28 +00:00 |
|
MerryMage
|
1ba2642742
|
Implement DC instructions
|
2018-02-11 23:12:28 +00:00 |
|
Lioncash
|
e12fa19142
|
A64: Implement NOT (vector)
|
2018-02-11 20:14:03 +00:00 |
|
MerryMage
|
1b836b6deb
|
IR: Implement FPMax, FPMin
|
2018-02-11 16:43:47 +00:00 |
|
MerryMage
|
94115d1775
|
A64: Implement FADD (vector), vector variant
|
2018-02-11 16:30:03 +00:00 |
|
MerryMage
|
24def19cd7
|
IR: Implement FPVectorAdd
|
2018-02-11 16:29:48 +00:00 |
|
MerryMage
|
9379d54a44
|
A64: Implement SSHLL, SSHLL2
|
2018-02-11 16:24:55 +00:00 |
|
MerryMage
|
a7e4202828
|
IR: Implement VectorSignExtend
|
2018-02-11 16:24:33 +00:00 |
|
MerryMage
|
ae7d118f22
|
A64: Implement DUP (element), vector variant
|
2018-02-11 14:34:13 +00:00 |
|
MerryMage
|
b87814ce88
|
load_store_multiple_structures: Improve IR codegen for selem == 1 case
|
2018-02-11 12:48:49 +00:00 |
|
MerryMage
|
6113346a5b
|
A64: Implement FSUB (vector)
|
2018-02-11 12:18:05 +00:00 |
|
MerryMage
|
8c6fce20d2
|
IR: Implement FPVectorSub
|
2018-02-11 12:17:53 +00:00 |
|
MerryMage
|
4df6c424df
|
Forward declare IR::Opcode and IR::Type where possible
|
2018-02-11 11:52:44 +00:00 |
|
MerryMage
|
09632954d7
|
A64: Implement CNT
|
2018-02-11 11:52:44 +00:00 |
|
MerryMage
|
c2c9ea85a5
|
IR: Implement VectorPopulationCount
|
2018-02-11 11:52:44 +00:00 |
|
MerryMage
|
0996d4fd2e
|
A64: Implement MLS (vector)
|
2018-02-11 11:04:46 +00:00 |
|
MerryMage
|
5319f6af95
|
A64: Implement MLA (vector)
|
2018-02-11 11:00:16 +00:00 |
|