MerryMage
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f87ecad5a4
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A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2018-02-04 13:09:57 +00:00 |
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MerryMage
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e5ce22aabc
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A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
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2018-02-04 12:49:40 +00:00 |
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Lioncash
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ccf9493653
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A64: Implement AESD
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2018-02-03 23:11:46 +00:00 |
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Lioncash
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33bc59c55a
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A64: Implement AESE
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2018-02-03 23:11:46 +00:00 |
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MerryMage
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a7209dc2f7
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IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
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2018-02-03 13:41:36 +00:00 |
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MerryMage
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2262b08a04
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A64: Implement INS (general)
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2018-02-03 13:07:00 +00:00 |
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MerryMage
|
3c140141db
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A64: Implement INS (element)
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2018-02-03 13:03:50 +00:00 |
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MerryMage
|
af5fb0a1a0
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A64: Implement SMOV
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2018-02-03 12:58:19 +00:00 |
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MerryMage
|
818b9a4673
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A64: Implement UMOV
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2018-02-03 12:55:53 +00:00 |
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MerryMage
|
9ea219e010
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basic_block: Fix bogus GCC maybe-uninitialized warning
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2018-02-03 03:04:44 +00:00 |
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MerryMage
|
64e37de179
|
A64: Implement FCVT
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2018-02-03 01:23:11 +00:00 |
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MerryMage
|
f1d2cdde34
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fuzz_with_unicorn: Skip instructions that need to be interpreted
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2018-02-03 01:22:40 +00:00 |
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MerryMage
|
2fd70e56ce
|
A64: Implement FMOV (scalar, immediate)
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2018-02-03 00:52:48 +00:00 |
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MerryMage
|
567c1b57fc
|
A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
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2018-02-02 22:39:24 +00:00 |
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MerryMage
|
c42ca435ba
|
A64: Implement FCMP, FCMPE
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2018-02-02 22:25:51 +00:00 |
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MerryMage
|
4728257d4e
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A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
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2018-02-02 22:04:09 +00:00 |
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MerryMage
|
fcabd95ad0
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IR: Merge U32 and U64 variants of FP instructions
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2018-02-02 21:55:23 +00:00 |
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MerryMage
|
6d9adb668e
|
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2018-02-02 21:10:30 +00:00 |
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MerryMage
|
cc40b83ed0
|
IR: Implement VectorSetElement{8,16,32,64}
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2018-02-02 21:00:12 +00:00 |
|
Lioncash
|
b608979be9
|
A64: Implement AESIMC and AESMC
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2018-02-02 17:35:16 +00:00 |
|
Lioncash
|
7fb386aa1c
|
A64: Implement CRC32
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2018-01-29 17:06:17 +00:00 |
|
MerryMage
|
e0ab098473
|
A32: data_processing: Remove !S assertions
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2018-01-28 12:59:52 +00:00 |
|
MerryMage
|
b96014b3b2
|
A32: Implement BKPT
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2018-01-28 12:59:52 +00:00 |
|
MerryMage
|
14910e53d3
|
A32: Add ExceptionRaised IR instruction and use it
|
2018-01-28 12:59:52 +00:00 |
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Lioncash
|
0216cbd2a5
|
A64: Implement CRC32C
|
2018-01-28 12:20:56 +00:00 |
|
MerryMage
|
2e14326fd5
|
assert: Use fmt in ASSERT_MSG
|
2018-01-28 00:00:58 +00:00 |
|
MerryMage
|
1f06ca80d4
|
a64_emit_x64: Perform RSB predictions
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2018-01-27 22:48:08 +00:00 |
|
MerryMage
|
3f6889f700
|
A32: Change UserCallbacks to be similar to A64's interface
|
2018-01-27 22:45:48 +00:00 |
|
MerryMage
|
9232be5553
|
ir_opt: Add A64 Get/Set Elimination Pass
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2018-01-27 00:38:43 +00:00 |
|
MerryMage
|
39b7625e9d
|
ir_emitter: Allow the insertion point for new instructions to be set
|
2018-01-27 00:38:43 +00:00 |
|
Lioncash
|
dbddb4858a
|
A64: Implement EXTR
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2018-01-26 22:07:48 +00:00 |
|
MerryMage
|
bda9148e71
|
A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
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2018-01-26 18:39:19 +00:00 |
|
MerryMage
|
0c1c82a937
|
IR: Implement IR instructions A64{Get,Set}S
|
2018-01-26 18:38:30 +00:00 |
|
Lioncash
|
8c013e7928
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
|
2018-01-26 17:06:48 +00:00 |
|
Lioncash
|
792cb91753
|
A64: Zero upper 64 bits in ORN if using the 64-bit variant
Resolves a TODO
|
2018-01-26 17:06:26 +00:00 |
|
MerryMage
|
a3af4dd218
|
load_store_register_unprivileged: bug: LDTRSW
|
2018-01-26 02:03:16 +00:00 |
|
MerryMage
|
06bea0ceaa
|
A64: Implement CMEQ (register, vector)
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2018-01-26 01:52:42 +00:00 |
|
MerryMage
|
f7e8a2259a
|
IR: Implement IR instructions VectorEqual{8,16,32,64,128}
|
2018-01-26 01:52:06 +00:00 |
|
Fernando Sahmkow
|
5ffd11d140
|
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
|
2018-01-26 00:57:56 +00:00 |
|
MerryMage
|
d99c99aabb
|
microinstruction: Missed A64{Read,Write}Memory128 from opcode information
|
2018-01-25 23:56:14 +00:00 |
|
James Rowe
|
0cc1bce1a8
|
Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
|
2018-01-25 17:46:14 +00:00 |
|
James Rowe
|
76aaa84687
|
A64: Fix bugs and address review comments
|
2018-01-25 17:46:14 +00:00 |
|
James Rowe
|
7825ae3a4f
|
Add missing returns
|
2018-01-25 17:46:14 +00:00 |
|
James Rowe
|
ddb5b3469d
|
A64: Implement Load/Store register (unprivileged)
|
2018-01-25 17:46:14 +00:00 |
|
MerryMage
|
314e020992
|
IR: Add IR instruction VectorZeroUpper
|
2018-01-24 17:11:13 +00:00 |
|
FernandoS27
|
d1664096f5
|
Implemented SDIV and UDIV instructions
|
2018-01-24 17:09:00 +00:00 |
|
MerryMage
|
8873d17db2
|
A64: Implement LDR/STR (immediate, SIMD&FP)
|
2018-01-24 16:28:18 +00:00 |
|
MerryMage
|
d6589fe3ee
|
IR: Add IR instructions A64Memory{Read,Write}128
This implementation only works on macOS and Linux.
|
2018-01-24 16:18:58 +00:00 |
|
MerryMage
|
5421c90216
|
IR: Add IR instruction VectorGetElement{8,16,32,64}
|
2018-01-24 16:18:58 +00:00 |
|
MerryMage
|
3932d6d695
|
IR: Add IR instruction ZeroExtendToQuad
|
2018-01-24 16:18:58 +00:00 |
|