Citra-emu/dynarmic-android
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561 Commits

Author SHA1 Message Date
MerryMage
f3e763a667 A64: Implement logical 2018-01-09 18:57:06 +00:00
MerryMage
f0c29feddb A64: Implement pcrel 2018-01-09 18:57:06 +00:00
MerryMage
8a8dcad250 A64: Implement addsub instructions 2018-01-09 18:57:06 +00:00
MerryMage
1431cedcaa A64: Implement ADD_shifted 2018-01-09 18:57:06 +00:00
MerryMage
ef6fd92fed A64: Backend framework 2018-01-09 18:57:06 +00:00
MerryMage
557fe60164 A64: Initial framework 2018-01-09 18:57:06 +00:00
MerryMage
512dae0361 IR: Compile-time type-checking of IR 2018-01-09 18:20:57 +00:00
MerryMage
b88b7ecbbf IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg 2018-01-09 18:20:57 +00:00
MerryMage
dbbbf4c331 Make IR->A32 LocationDescriptor conversion explicit 2018-01-09 18:20:57 +00:00
MerryMage
be094ff150 Final A32 refactor 2018-01-09 18:20:57 +00:00
MerryMage
42c83fadce IR: Split off A32 specific opcodes 2018-01-09 18:20:57 +00:00
MerryMage
f5402c8d82 A32: Split off A32 specific IREmitter 2018-01-09 18:20:57 +00:00
MerryMage
3e569047a5 Label A32 specific code appropriately 2018-01-09 18:20:57 +00:00
MerryMage
c823ecf524 interface: Allow saving and storing of contexts 2017-12-12 14:24:07 +00:00
MerryMage
976a098bf6 jit_state: Split off CPSR.NZCV 2017-12-12 14:24:07 +00:00
MerryMage
2e6eda226c jit_state: Split off CPSR.{E,T} 
This allows us to improve code-emission for PopRSBHint. We also improve
code emission other terminals at the same time.
 2017-12-12 14:23:34 +00:00
MerryMage
4110494ac4 emit_x64: Use boost::icl::interval_map to speed up ranged invalidation 2017-12-06 20:55:29 +00:00
MerryMage
bb87d2540c Remove unnecessary use of boost::make_optional 
Closes #119.
 2017-11-28 20:56:54 +00:00
MerryMage
5f64bf9cfa decoder_detail: Lambda captures may be unused if iota is an empty sequence 
Closes #120
 2017-11-28 19:48:32 +00:00
MerryMage
1d75664afd Remove UNUSED macro 2017-11-28 19:44:33 +00:00
MerryMage
67c8e6e695 microinstruction: Remove DecrementRemainingUses 2017-11-27 20:10:23 +00:00
MerryMage
6776f83a0c basic_block: Add inst address and use count to DumpBlock 
This additional output assists with debugging.
 2017-11-27 19:51:54 +00:00
MerryMage
311b6609aa Implement IR instruction PackedSelect, reimplement SEL 2017-11-25 16:33:48 +00:00
MerryMage
c421a137c0 VCMP and VCMPE were the other way around 
- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
 2017-11-22 17:45:37 +00:00
MerryMage
29471be317 Standardize location of storage-class specifiers: Place at beginning of declarations 
Justification: C99 specifies that doing otherwise is an obsolescent feature.
 2017-09-29 01:23:45 +01:00
MerryMage
993e142c6b disassembler: Fix RegList 2017-08-05 01:57:29 +01:00
MerryMage
6197bde0fc disassembler_arm: Fix disassembly of LDRH (reg) 2017-07-30 18:45:55 +01:00
MerryMage
599a613fea Move SEL from status_register_access to misc 2017-04-25 13:57:27 +01:00
MerryMage
50bb317104 parallel: UQADD8 and UQADD16 are unpredictable when {d|n|m} == 15 2017-04-25 13:45:31 +01:00
MerryMage
7639dfea51 coprocessor: Use && instead of & with boolean arguments 2017-04-22 15:05:31 +01:00
MerryMage
1c21ae6bcd saturated: Implement QASX, QSAX, UQASX, UQSAX 2017-04-10 10:21:51 +01:00
MerryMage
523ae542f4 microinstruction: Implement HasAssociatedPseudoOperation 2017-04-04 13:10:50 +01:00
MerryMage
05e97058c3 parallel: Add and Subtract with Exchange improvements 
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
 2017-03-24 15:56:24 +00:00
Lynn
fd068ed6b8 Ranged cache invalidation 2017-03-20 11:58:25 +00:00
MerryMage
92a01b0cd8 Prefer ASSERT to DEBUG_ASSERT 2017-02-26 23:30:40 +00:00
MerryMage
bbeea72eba ir_opt: Remove redundant shift instructions 2017-02-26 15:28:14 +00:00
MerryMage
4ed8ee7489 microinstruction: Void arguments when invalidating instruction 2017-02-18 21:29:23 +00:00
MerryMage
7fa5845c1f extension: Implement SXTAB16 and SXTB16 2017-02-18 20:14:44 +00:00
MerryMage
73d1cf36c3 extension: Simplify UXTB16 2017-02-18 20:14:39 +00:00
MerryMage
6edcfeba0b extension: Simplify rotation code 2017-02-18 20:14:37 +00:00
MerryMage
cc9d2c4603 saturated: Implement SSAT16 and USAT16 2017-02-18 17:43:57 +00:00
MerryMage
358cf7c322 vfp: Implement vectorized VFP instructions 2017-02-18 01:13:25 +00:00
MerryMage
f2dd82967f load_store: Simplify implementation 
* Remove dead code
* Standardise code style with rest of code base
 2017-02-16 22:28:56 +00:00
MerryMage
5a20a37d3f arm/fpscr: Correct Stride implementation 2017-02-11 12:13:57 +00:00
MerryMage
033e8b9b1e vfp: Rename variables a, b, c to more sensible names 2017-02-06 21:14:36 +00:00
MerryMage
642ccb0f66 ir/value: Support U16 immediates 2017-01-29 22:58:11 +00:00
MerryMage
5f7ffe0d0b microinstruction: Implement Inst::AreAllArgsImmediates 2017-01-29 22:56:59 +00:00
MerryMage
22804dc6a5 microinstruction: Arguments of Inst::Use and Inst::UndoUse should be const 2017-01-29 22:53:46 +00:00
MerryMage
1d4446cad5 microinstruction: Removed unnecessary reference from argument of Inst::ReplaceUsesWith 2017-01-29 22:52:33 +00:00
MerryMage
e3bc7d039f Implement CDP, LDC, MCR, MCRR, MRC, MRRC, STC 2017-01-08 14:56:06 +00:00